Achronix Speedster22i SerDes - Manual (Page 88)

For our sample design, we have defined data-rate=10.3125gbps and data-width=20. For this
higher-rate, the wide-bus architecture will be used. In other words, 40-bits data will be
transmitted to and received from SerDes. The frequency for both TX and RX clock will then
be 257.81 MHz:
Equation 2
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 =
𝐷𝑎𝑡𝑎_𝑟𝑎𝑡𝑒
𝑑𝑎𝑡𝑎_𝑡𝑟𝑎𝑛𝑠𝑚𝑖𝑠𝑠𝑖𝑜𝑛_𝑤𝑖𝑑𝑡ℎ =
10.3125
40
= 257.81 𝑀𝐻
We should have clocks toggling at ~129 MHz for both ln0_TXclk_div2 and ln0_RXclk_div2.
1) It’s mandatory for all SerDes lanes instantiated in the design to have a reference clock
going to them. If two SerDes lanes are instantiated in a design, BOTH lanes will need a
reference clock even if only one of them is being used.
2) ALL reference clocks should be running on ALL the serdes lanes before programming
the bitstream (and they should be running after programming as well).
3) For certain modes (Deskew), all the reference clocks should be coming from the same
clock source.
Variants of the Simple Design
In the earlier section, a sample design has been presented, the description of which is given in
the listing below. This section details the preparation of the designs that use different sets of
components from PCS block. This section will detail only the derivatives, as compared to the
steps followed in creating the simple design in the earlier section: simple_serdes_design.
Understanding the steps detailed in this section therefore requires the understanding of the
steps listed for creating simple_serdes_design.
Design using Clock Compensation (EFIFO):
In simple_serdes_design, we disable the PCS block that takes care of clock compensation:
EFIFO. The preparation of a design with clock compensation is presented here.
The design with clock compensation enabled is called simple_serdes_design_efifo. The
specifications for this design are listed below
Design name : simple_serdes_design_efifo
Objective : Send data from fabric to SerDes and read-back data using external loopback.
Data rate : 10.3125 Gbps
Standard : Generic
Number of lanes : 1
Placement : South lane# 8
Ref. clock : 156.25 Mhz
Data width : 40
PCS blocks used :
8b/10b encoder
8b/10b decoder
Symbol alignment: Automatic mode
Clock compensation (EFIFO) is enabled
88 UG028, July 1, 2014