Achronix Speedster22i SerDes - Manual (Page 78)

the placement of SerDes-Reset signal (ln0_rst_hard); TX-ready status signal (ln0_TX_ready)
and the placement of the sbus-clock that is required to set internal-loopback through sbus
interface
# Manually entered Design-specific: For providing sbus-clock for sbus-interface
# The pin (pad0_clk_bank_se) refers to the clock-supply used in Achronix Validation Board.
set_placement -fixed -batch {p:i_sclk} {d:pad0_clk_bank_se}
#SerDes reset
set_placement -batch -fixed {p:ln0_rst_hard} { d:pad0_clk_bank_nw }
# TX_ready signal is brought to a LED (active-low)
set_placement -batch -fixed {p:ln0_pma_TXready} { d:pad_ws_byteio9_dq3 }
Timing Constraints
Using the directory structure defined earlier, the timing constraints will be in the file
src/constraints/ace_constraint.sdc. The ACE GUI generates template for timing constraints
used for the respective SerDes design. For instance, for simple_serdes_design, timing
constraint has been generated as src/ace/simple_serdes_design_wrapper.sdc file (“Figure 35:
Generating the Wrapper Filess”). This ACE-generated file can be used as a template for
defining the timing constraints of a SerDes design. However, the user must manually enter
the design related constraints, which are not generated by ACE for obvious reasons.
The simple_serdes_design that is being described here requires such clocks that the user
needs to provide. In the following code-snippet, the SerDes reference clocks from “Table 20:
Signals passed between the SerDes Instance and the Top-Level module” as well as snapshot
clocks have been added to the ACE-generated constraints. (Please refer to the ACE User
Document for further details on using snapshot debugging tool into a design.)
#Reference clocks
# Manually entered Design-specific: For providing 156.25 reference clocks to SerDes
create_clock -period 6.4 refclkp
create_clock -period 6.4 refclkn
# Manually entered Design-specific: For providing 50MHz clock to sbus-clock.
create_clock -period 20 i_sclk
# Manually entered Design – specific: SNAPSHOT clocks
# Clock for snapshot and for jtap
create_clock -period 100 tck
# Uset-entered
set_clock_groups –asynchronous –group {tck }
# From ACE – generated constraint file:
# Lane RX Clocks
# Period (ns) = 1/(RX data rate / RX 8b10b-encoded data width)
# 1.9393939393939394 = 1/(10.3125 / 20.0)
# Unrelated Clock Mode: All lane-to-lane clocks are unrelated EXCEPT between the TX clocks -
Elastic buffer is disabled
create_clock -period 1.93939393939394 iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_RX_data_clk
create_clock -period 1.93939393939394 iSERDES.x_ch0.u_serdes_wrap.u_serdes/o_TX_data_clk
# Lane Clock Divider Generated Clocks
# Unrelated Clock Mode: All lane-to-lane clocks are unrelated - Elastic buffer is disabled
78 UG028, July 1, 2014