List of Tables
Table 1: SerDes Standards........................................................................................................................................................ 9
Table 2: Symbol Slip Paramaters........................................................................................................................................... 27
Table 3: Shift Limit .................................................................................................................................................................. 31
Table 4: List of Important Interface Signals for bit slider .................................................................................................. 32
Table 5: PIPE Interface Paramaters ....................................................................................................................................... 35
Table 6: PRBS Patterns in PMA ............................................................................................................................................. 40
Table 7: PRBS Patterns in the PCS ........................................................................................................................................ 40
Table 8: Analog latency as a function of databus width .................................................................................................... 42
Table 9: Latency across the PCS blocks ................................................................................................................................ 43
Table 10: Supported Transmitter (TX) Features .................................................................................................................. 45
Table 11: Supported Receiver (RX) Features ....................................................................................................................... 47
Table 12: Entry fields for Overview page ............................................................................................................................ 53
Table 13: RX PMA Equalization ............................................................................................................................................ 59
Table 14: RX PMA PLL Settings ............................................................................................................................................ 61
Table 15: TX PMA Driver Settings ........................................................................................................................................ 62
Table 16: TX PMA PLL Settings ............................................................................................................................................ 63
Table 17: RX PCS Settings ...................................................................................................................................................... 64
Table 18: Symbol Alignment Settings (PCS) ....................................................................................................................... 66
Table 19: TX PCS Settings ...................................................................................................................................................... 69
Table 20: Signals passed between the SerDes Instance and the Top-Level module ...................................................... 73
Table 21: Modifications for simple_serdes_design_efifo (RX PCS Settings)................................................................... 89
Table 22: Operating Conditions .......................................................................................................................................... 104
Table 23: DC and AC Switching Characteristics .............................................................................................................. 105
Table 24: Jitter ........................................................................................................................................................................ 106
Table 25: Return Loss ........................................................................................................................................................... 107
Table 26: DC and AC Switching Characteristics .............................................................................................................. 108
Table 27: Receiver (RX) Eye Diagram Specification ......................................................................................................... 110
Table 28: Return Loss ........................................................................................................................................................... 111
Table 29: Reference Clock Electrical Speficiations ............................................................................................................ 112
Table 30: Reference Clock Jitter Specification ................................................................................................................... 112
6
UG028, July 1, 2014
