Achronix Speedster22i SerDes - Manual (Page 55)

Entry field Purpose Available Options Choice made
SerDes Lanes The specific lane used.
Achronix FPGA has 64
SerDes lanes, 32 each
on North and South
sides. When
North/South selected
from Chip Edge combo-
box, option is given for
each of the 32 lanes on
corresponding side. *2
8
*1 The users may not use any combination of (a) TX (RX) data rate and (b) reference clock frequency.
This is due to the constraint that the Voltage Controlled Oscillator (VCO) clock rate derived from the
TX and RX data rates must integer multiple of the ref clock frequency. If the user’s choices do not
comply with this constraint, the error will be reported in IP problems window, as shown in Figure 27:
Issues with Setting TX/RX data rate and reference clock frequency
*2 Refer to the Chapter-“Overview” of this document for further details on the locations of SerDes
lanes in an Achronix FPGA.
*3 The user also needs to use identical values for reference clock frequency for both TX and RX.
Note: As the user goes through the ACE GUI, some entry fields may become disabled based
on the earlier choices. Furthermore, some parameters become fixed (and unavailable for
change) based on the earlier choices. For instance, the Enable Channel Bonding check-box is
disabled for the simple_serdes_design that uses a single lane. “Figure 27: Issues with Setting
TX/RX data rate and reference clock frequency” further emphasizes this. In this Figure, when
the user chooses XAUI as the SerDes standard, all the fields except for termination and
operating mode are set at pre-defined values and become unavailable for changes.
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