ADLINK DAQe-2214 - Manual (Page 89)

Operation Theory 77
tion on the internal timing signals. Physically, the signal routings
are accomplished in the FPGA. Cards that are connected together
through the SSI trigger bus can still achieve synchronization on
the four/six timing signals.
The SSI Mechanism
The DAQ-/DAQe-2213/2214 adopts a master-slave configura-
tion for SSI. In a system, for each timing signal, there shall be
only one master while all other cards are SSI slaves or with SSI
function disabled.
For each timing signal, the SSI master does not have to be in a
single card. For example, if you want to synchronize the A/D
operation through the ADCONV signal for four DAQ-/DAQe-
2213/2214 cards, Card 1 is the master while Card 2, 3, and 4
are slaves. Card 1 receives an external digital trigger to start
the post trigger mode acquisition. The SSI setting could be:
X
Set the SSI_ADCONV signal of Card 1 to be the master.
X
Set the SSI_ADCONV signals of Card 2, 3, and 4 to be the
slaves.
X
Set the external digital trigger for Card 1’s A/D operation.
X Set the SI_counter and the post scan counter (PSC) of all
other cards.
X
Start DMA operations for all cards so all the cards are wait-
ing for the trigger event.
When the digital trigger condition of Card 1 occurs, Card 1
internally generates the ADCONV signal and outputs this
ADCONV signal to the SSI_ADCONV signal of Card 2, 3 and 4
through the SSI connector. Thus we can achieve 4-channel
simultaneous acquisition.
You could arbitrarily choose each of the six/four timing signals
as the SSI master from any one of the cards. The SSI master
can output the internal timing signals to the SSI slaves. With
the SSI, you can achieve better card-to-card synchronization.
Note that when power-up or reset, the DAQ timing signals are
reset to use the internal generated timing signals.