Altera Arria 10 Avalon-ST - Manual (Page 113)

Configuration Space Register Access Timing
Figure 6-37: tl_cfg_ctl Timing
The following figure shows typical traffic on the
tl_cfg_ctl
bus. The
tl_cfg_add
index increments on
the rising edge of the
pld_clk
. The address specifies which Configuration Space register data value is
being driven onto
tl_cfg_ctl
.
coreclkout_hip
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
D E F 0 1 2 3
00000084 00000000 28100000 08000000 00000002
Configuration Space Register Access
The
tl_cfg_ctl
signal is a multiplexed bus that contains the contents of Configuration Space registers as
shown in the figure below. Information stored in the Configuration Space is accessed in round robin
order where
tl_cfg_add
indicates which register is being accessed. The following table shows the layout
of configuration information that is multiplexed on
tl_cfg_ctl
.
UG-01145_avst
2015.05.04
Configuration Space Register Access Timing 6-47
Interfaces and Signal Descriptions Altera Corporation
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