Altera Arria 10 Avalon-ST User Manual
Page 25
a. The working directory shown is correct. You do not have to change it.
b. For the project name, click the browse button browse to the synthesis directory that includes your
Qsys project,
<working_dir>/ep_g1x8/synth
and click Choose. If the top-level design entity and Qsys
system names are identical, the Quartus II software treats the Qsys system as the top-level design
entity.
c. For What is the name of this project, select your variant name
ep_g1x8
. Then click Open. If the
top-level design entity and Qsys system names are identical, the Quartus II software treats the Qsys
system as the top-level design entity.
d. For Project Type select Empty project.
5. Click Next to display the Add Files page.
6. Complete the following steps to add the Quartus II IP File ( .qip )to the project:
a. Click the browse button. The Select File dialog box appears.
b. Browse up one level to
<working_dir>/ep_g1x8/
button.
c. In the Files of type list, select IP Variation Files (*.qip *.sip).
d. Click
ep_g1x8.qip
and then click Open.
e. On the Add Files page, click Add.
7. Click Next to display the Device page.
8. On the Family & Device Settings page, choose the following target device family and options:
a. In the Family list, select Arria 10 (GX/SX/GT).
b. In the Devices list, select Arria 10 All.
c. In the Devices list, select All.
d. In the Available devices list, select the appropriate device. For Arria 10 ES2 development kits, select
10AX115S1F45I3SGE2.
9. Click Next to close this page and display the EDA Tool Settings page.
10.From the Simulation list, select ModelSim
®
. From the Format list, select the HDL language you
intend to use for simulation.
11.Click Next to display the Summary page.
12.Check the Summary page to ensure that you have entered all the information correctly.
13.Click Finish to create the Quartus II project.
14.Before compiling, you must assign I/O standards to the pins of the device. Refer to Making Pin
Assignments to Assign I/O Standard to Serial Data Pins for instructions.
15.You must connect the
pin_perst
reset signal to the correcsponding
nPERST
pin of the device. Refer to
the definition of
pin_perst
in the Reset, Status, and Link Training Signals section for more informa‐
tion.
16.Next, set the value of the
test_in
bus to a value that is compatible for hardware testing. In Qsys design
example provided,
test_in
is a top-level port.
a. Comment out the
test_in
port in the top-level Verilog generated file.
b. Add the following declaration,
wire[31:0] test_in
, to the same top-level Verilog file.
c. Assign
hip_ctrl_test_in = 32'hA8
.
d. Connect
test_in
to
hip_ctrl_test_in
.
Refer to the definition of
test_in
in the Test Signals section for more information about the bits of the
test_in
bus.
17.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐
tion. The Quartus II software then performs all the steps necessary to compile your design.
2-6
Compiling the Design in the Qsys Design Flow
UG-01145_avst
2015.05.04
Altera Corporation
Getting Started with the Arria 10 Hard IP for PCI Express