Altera Arria 10 Avalon-ST - Manual (Page 87)

Signal Direction Description
tx_cred_fc_hip_
cons[5:0]
Output Asserted for 1 cycle each time the Hard IP consumes a credit.
These credits are from messages that the Hard IP for PCIe
generates for the following reasons:
• To respond to memory read requests
• To send error messages
This signal is not asserted when an Application Layer credit is
consumed. The Application Layer must keep track of its own
consumed credits. To calculate the total credits consumed, the
Application Layer must add its own credits consumed to those
consumed by the Hard IP for PCIe. The credit signals are valid
after the
dlup
(data link up) is asserted.
The 6 bits of this vector correspond to the following 6 types of
credit types:
• [5]: posted headers
• [4]: posted data
• [3]: non-posted header
• [2]: non-posted data
• [1]: completion header
• [0]: completion data
During a single cycle, the IP core can consume either a single
header credit or both a header and a data credit.
tx_cred_fc_
infinite[5:0]
Output When asserted, indicates that the corresponding credit type has
infinite credits available and does not need to calculate credit
limits. The 6 bits of this vector correspond to the following 6
types of credit types:
• [5]: posted headers
• [4]: posted data
• [3]: non-posted header
• [2]: non-posted data
• [1]: completion header
• [0]: completion data
tx_cred_fc_sel[1:0] Input Signal to select between the
tx_cred_hdr_fc
and
tx_cred_
data_fc
outputs. The following encoding are defined:
• 2'b00: Output Posted credits
• 2'b01: Output Non-Posted credits
• 2'b10: Output Completions
tx_cred_hdr_fc[7:0] Output Header credit limit for the FC posted writes. Each credit is 20
bytes.
UG-01145_avst
2015.05.04
Avalon-ST TX Interface 6-21
Interfaces and Signal Descriptions Altera Corporation
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