Altera Arria 10 Avalon-ST - Manual (Page 5)

Interrupts ....................................................................................................................................... 11-4
PIPE ................................................................................................................................................ 11-4
Transaction Layer ..................................................................................................................................... 11-5
Configuration Space ..................................................................................................................... 11-6
Error Checking and Handling in Configuration Space Bypass Mode ...................................11-7
Protocol Extensions Supported .................................................................................................11-10
Data Link Layer .......................................................................................................................................11-10
Physical Layer ..........................................................................................................................................11-12
Transaction Layer Protocol (TLP) Details........................................................12-1
Supported Message Types ........................................................................................................................12-1
INTX Messages ..............................................................................................................................12-1
Power Management Messages .................................................................................................... 12-2
Error Signaling Messages .............................................................................................................12-3
Locked Transaction Message ...................................................................................................... 12-4
Slot Power Limit Message ............................................................................................................12-4
Vendor-Defined Messages ...........................................................................................................12-4
Hot Plug Messages ........................................................................................................................12-5
Transaction Layer Routing Rules ........................................................................................................... 12-6
Receive Buffer Reordering .......................................................................................................................12-7
Using Relaxed Ordering ...............................................................................................................12-9
Throughput Optimization................................................................................ 13-1
Throughput of Posted Writes ................................................................................................................. 13-3
Throughput of Non-Posted Reads ......................................................................................................... 13-3
Design Implementation.................................................................................... 14-1
Making Pin Assignments to Assign I/O Standard to Serial Data Pins ..............................................14-1
Recommended Reset Sequence to Avoid Link Training Issues ......................................................... 14-1
SDC Timing Constraints.......................................................................................................................... 14-2
Optional Features..............................................................................................15-1
Configuration via Protocol (CvP) .......................................................................................................... 15-1
ECRC .......................................................................................................................................................... 15-2
ECRC on the RX Path .................................................................................................................. 15-2
ECRC on the TX Path .................................................................................................................. 15-3
Hard IP Reconfiguration ..................................................................................16-1
Testbench and Design Example ....................................................................... 17-1
Endpoint Testbench ................................................................................................................................. 17-2
Root Port Testbench .................................................................................................................................17-3
Chaining DMA Design Examples .......................................................................................................... 17-4
BAR/Address Map ........................................................................................................................17-8
Getting Started with the Arria 10 Hard IP for PCI Express with the Avalon-ST Interface TOC-5
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