Modifying the example design, Modifying the example design -7 – Altera Arria 10 Avalon-ST User Manual

Page 26

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Files Generated for Altera IP Cores
Figure 2-3: IP Core Generated Files

<your_testbench>_tb.csv

<your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Contains assingments for IP simulation files

<your_ip>.v or .vhd
Top-level IP synthesis file

<your_ip>.v or .vhd
Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines simulation scripts for multiple cores

<your_ip>_tb.qsys
Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<project directory>

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

<EDA tool name>

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<HDL files>

<HDL files>

<your_ip> n

IP variation files

testbench files

Related Information

Making Pin Assignments to Assign I/O Standard to Serial Data Pins

on page 14-1

Test Signals

on page 6-62

Reset, Status, and Link Training Signals

on page 6-31

Generating the Testbench

on page 2-3

Simulating the Example Design

on page 3-5

Simulating the Example Design

on page 3-5

Modifying the Example Design

To use this example design as the basis of your own design, replace the Chaining DMA Example shown in

the following figure with your own Application Layer design. Then modify the Root Port BFM driver to

generate the transactions needed to test your Application Layer.

UG-01145_avst

2015.05.04

Modifying the Example Design

2-7

Getting Started with the Arria 10 Hard IP for PCI Express

Altera Corporation

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