Altera Arria 10 Avalon-ST - Manual (Page 3)

Parameter Settings.............................................................................................. 4-1
System Settings ............................................................................................................................................4-1
Base Address Register (BAR) and Expansion ROM Settings ............................................................... 4-5
Base and Limit Registers for Root Ports .................................................................................................. 4-7
Device Identification Registers ..................................................................................................................4-7
PCI Express and PCI Capabilities Parameters ........................................................................................4-8
Device Capabilities ..........................................................................................................................4-9
Error Reporting .............................................................................................................................4-10
Link Capabilities ........................................................................................................................... 4-11
MSI and MSI-X Capabilities ........................................................................................................4-12
Slot Capabilities .............................................................................................................................4-13
Power Management ......................................................................................................................4-14
Vendor Specific Extended Capability (VSEC).......................................................................................4-15
PHY Characteristics ................................................................................................................................. 4-15
Physical Layout of Hard IP In Arria 10 Devices.................................................5-1
Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates..............................................5-4
Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates............................................5-5
Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate...................................... 5-7
Interfaces and Signal Descriptions .................................................................... 6-1
Avalon-ST RX Interface ............................................................................................................................. 6-2
Avalon-ST RX Component Specific Signals ................................................................................6-4
Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface ......................................6-6
Data Alignment and Timing for the 128-Bit Avalon-ST RX Interface ................................. 6-11
Data Alignment and Timing for 256-Bit Avalon-ST RX Interface ........................................6-15
Tradeoffs to Consider when Enabling Multiple Packets per Cycle ....................................... 6-15
Avalon-ST TX Interface ...........................................................................................................................6-16
Avalon-ST Packets to PCI Express TLPs ...................................................................................6-22
Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface ................................... 6-22
Data Alignment and Timing for the 128-Bit Avalon-ST TX Interface ................................. 6-25
Data Alignment and Timing for the 256-Bit Avalon-ST TX Interface ................................. 6-28
Root Port Mode Configuration Requests .................................................................................. 6-31
Clock Signals ..............................................................................................................................................6-31
Reset, Status, and Link Training Signals.................................................................................................6-31
ECRC Forwarding .....................................................................................................................................6-36
Error Signals .............................................................................................................................................. 6-36
Interrupts for Endpoints ..........................................................................................................................6-37
Interrupts for Root Ports ......................................................................................................................... 6-38
Completion Side Band Signals ................................................................................................................ 6-38
Parity Signals ............................................................................................................................................. 6-41
LMI Signals ................................................................................................................................................ 6-42
Transaction Layer Configuration Space Signals ...................................................................................6-44
Configuration Space Register Access Timing ...........................................................................6-47
Configuration Space Register Access ......................................................................................... 6-47
Getting Started with the Arria 10 Hard IP for PCI Express with the Avalon-ST Interface TOC-3
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