Zilog Z80230 - Manual (Page 11)

SCC/ESCC
User Manual
UM010903-0515 General Description
4
– Improved functionality to ease sending back-to back frames
– Automatic SDLC opening Flag transmission*
– Automatic Tx Underrun/EOM Latch reset in SDLC mode*
– Automatic /RTS deactivation*
– TxD pin forced “H” in SDLC NRZI mode after closing flag*
– Complete CRC reception*
– Improved response to Abort sequence in status FIFO
– Automatic Tx CRC generator preset/reset
– Extended read for write registers*
– Write data setup timing improvement
• Improved AC timing:
– Three to 3.5 PCLK access recovery time.
– Programmable /DTR//REQ timing*
– Elimination of write data to falling edge of /WR setup time requirement
– Reduced /INT timing
• Other features include:
– Extended read function to read back the written value to the write registers*
– Latching RR0 during read
– RR0, bit D7 and RR10, bit D6 now has reset default value
Some of the features listed above are available by default, and some of them (features with “*”)
are disabled on default.
ESCC (Enhanced SCC) is pin and software compatible to the CMOS version, with the following
additional enhancements.
• Deeper transmit FIFO (4 bytes)
• Deeper receive FIFO (8 bytes)
• Programmable FIFO interrupt and DMA request level
• Seven enhancements to improve SDLC link layer supports:
– Automatic transmission of the opening flag
– Automatic reset of Tx Underrun/EOM latch
– Deactivation of /RTS pin after closing flag
– Automatic CRC generator preset
– Complete CRC reception
– TxD pin automatically forced high with NRZI encoding when using mark idle
– Status FIFO handles better frames with an ABORT