Zilog Z80230 - Manual (Page 34)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
27
Z85X30 Interface Timing
Two control signals, /RD and /WR, are used by the Z85X30 to time bus transactions. In addition,
four other control signals, /CE, D//C, A//B and /INTACK, are used to control the type of bus trans-
action that occurs. A bus transaction starts when the addresses on D//C and A//B are asserted
before /RD or /WR fall (AC Spec #6 and #8). The coincidence of /CE and /RD or /CE and /WR
latches the state of D//C and A//B and starts the internal operation. The /INTACK signal must have
been previously sampled High by a rising edge of PCLK for a read or write cycle to occur. In addi-
tion to sampling /INTACK, PCLK is used by the interrupt section to set the IP bits.
The Z85X30 generates internal control signals in response to a register access. Since /RD and /WR
have no phase relationship with PCLK, the circuitry generating these internal control signals pro-
vides time for metastable conditions to disappear. This results in a recovery time related to PCLK.
This recovery time applies only between transactions involving the Z85X30, and any intervening
transactions are ignored. This recovery time is four PCLK cycles (AC Spec #49), measured from
the falling edge of /RD or /WR in the case of a read or write of any register.
WR6 X X X X X X X X X X X X X X X X
WR7 X X X X X X X X X X X X X X X X
WR7'* 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
WR9 1 1 0 0 0 0 X X X X 0 X X X X X
WR10 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 0
WR11 0 0 0 0 1 0 0 0 X X X X X X X X
WR12 X X X X X X X X X X X X X X X X
WR13 X X X X X X X X X X X X X X X X
WR14 X X 1 1 0 0 0 0 X X 1 0 0 0 X X
WR15 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0
RR0 X 1 X X X 1 0 0 X 1 X X X 1 0 0
RR1 0 0 0 0 0 1 1 X 0 0 0 0 0 1 1 X
RR3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RR10 0 X 0 0 0 0 0 0 0 X 0 0 0 0 0 0
Note: *WR7' is available only on the Z80230.
Z80X30 Register Reset Values (Continued)
Hardware RESET Channel RESET
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0