Zilog Z80230 User Manual
Page 58
SCC/ESCC
User Manual
UM010903-0515
Interfacing the SCC/ESCC
51
When WR7' D5=1 (the default case), the ESCC will generate a transmit interrupt when the Trans-
mit FIFO becomes completely empty. The transmit interrupt occurs when the data in the exit loca-
tion of the Transmit FIFO loads into the Transmit Shift Register and the Transmit FIFO becomes
completely empty. This mode minimizes the frequency of transmit interrupts by writing 4 bytes to
the Transmit FIFO upon each entry to the interrupt will become set when WR7' D5=1. The TBE
bit RR0 bit D2 will become set whenever the entry location of the Transmit FIFO becomes empty.
The TBE bit will reset when the entry location becomes full. The TBE bit in a sense translates to
meaning “Transmit Buffer Not Full” for the ESCC only, as the TBE bit will become set whenever
the entry location of the Transmit FIFO becomes empty. This bit may be polled at any time to
determine if a byte can be written to the FIFO.
on page 53 displays when the TBE bit will
become set. WR7' bit D5 is set to one by a hardware or channel reset.
When WR7' D5=0, the TxIP bit is set when the entry location of the Transmit FIFO becomes
empty. In this mode, only one byte is written to the Transmit FIFO at a time for each transmit
interrupt. The ESCC will generate transmit interrupts when there are 3 or fewer bytes in the FIFO,
and will continue to do so until the FIFO is filled. When WR7' D5=0, the transmit interrupt is reset
momentarily when data is loaded into the entry location of the Transmit FIFO. Transmit interrupt
is not generated when the entry location of the Transmit FIFO is filled. The transmit interrupt is
generated when the data is pushed down the FIFO and the entry location becomes empty (approx-
on page 52 displays when the transmit interrupts will become set
when WR7' D5=0. Again, the TBE bit is not dependent on the state of WR7' bit D5 nor the trans-
mit interrupt status, and will respond exactly the same way as mentioned above.
53 displays when the TBE bit will become set.
When WR7' D5=0. only one byte is written to the FIFO at a time, when there are three or
fewer bytes in FIFO. Thus, for the ESCC multiple interrupts are generated to fill the FIFO.
To avoid multiple interrupts, one can poll the TBE bit (RR0 D2) after writing each byte.
While transmit interrupts are enabled, the ESCC sets the TxIP when the transmit buffer reaches the
condition programmed in WR7' bit D5. This means that the transmit buffer must have been written
to before the TxIP is set. Thus, when transmit interrupts are first enabled, the transmit IP is not set
until the programmed interrupting condition is met.
The TxIP is reset either by writing data to the transmit buffer or by issuing the Reset Tx Int Pend-
ing command in WR0. Ordinarily, the response to a transmit interrupt is to write more data to the
ESCC; however, if there is no more data to be transmitted at that time, it is the end of the frame.
The Reset Tx Int command is used to reset the TxIP and clear the interrupt. For example, at the
end of a frame or block of data where the CRC is to be sent next, the Reset Tx Int Pending com-
mand should be issued after the last byte of data has been written to the ESCC.
In synchronous modes, one other condition can cause the TxIP to be set. This occurs at the end of
a transmission after the CRC is sent. When the last bit of the CRC has cleared the Transmit Shift
Register and the flag or sync character is loaded into the Transmit Shift Register, the ESCC sets
the TxIP. Data for the new frame or block to be transmitted may be written at this time. In this par-
ticular case, the Transmit Buffer Empty bit in RR0 and the TxIP are set.
Note: