Scc/escc user manual – Zilog Z80230 User Manual
Page 249
SCC/ESCC
User Manual
UM010903-0515
Application Notes
242
Program Example – Z180 CPU Macro Instructions (Continued)
bcr1l:
equ
2eh
; DMA Byte Count Reg Ch1-low
bcr1h:
equ
2fh
; DMA Byte Count Reg Ch1-high
dstat:
equ
30h
; DMA Stat Reg
dmode:
equ
31h
; DMA Mode Reg
dcntl:
equ
32h
; DMA/WAIT Control Reg
;System Control Registers
il:
equ
33h
; INT Vector Low Reg
itc:
equ
34h
; INT/TRAP Cont Reg
rcr:
equ
36h
; Refresh Cont Reg
cbr
equ
38h
; MMU Common Base Reg
bbr:
equ
39h
; MMU Bank Base Reg
cbar:
equ
3ah
; MMU Common/Bank Area Reg
omcr:
equ
3eh
; Operation Mode Control Reg
icr:
equ
3fh
; I/O Control Reg
?b
equ
0
?c
equ
1
?d
equ
2
?e
equ
3
?h
equ
4
?l
equ
5
?a
equ
7
??bc
equ
0
??de
equ
1
??hl
equ
2
??sp
equ
3
slp
macro
db
11101101B
db
01110110B
endm
mlt
macro
?r
db
11101101B
db
01001100B+(??&?r AND 3) SHL 4
endm
in0
macro
?r, ?p
out0
macro
?p, ?r
db
11101101B
db
00000001B+(?&?r AND 7) SHL 3
db
?p
endm
otim
macro
db
11101101B