Zilog Z80230 - Manual (Page 122)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
115
necessary to reset the WR10 D3 to idle flag, wait 8-bit times, and then write data to the transmitter.
It is necessary to wait eight bit times before writing data because ‘1s’ are transmitted eight at a
time and all eight must leave the Transmit Shift register before a flag is loaded.
The ESCC has two improvements over the NMOS/CMOS version to control the transmission of
the flag at the beginning of a frame. Additionally, the ESCC has improved features to ease the han-
dling of SDLC mode of operation, including a function to deactivate the /RTS signal at the end of
the packet automatically. For these features, see ESCC Enhancements for SDLC Transmit on page
118.
The number of bits per transmitted character is controlled by bits D6 and D5 of WR5 and the way
the data is formatted within the transmit buffer. The bits in WR5 allow the option of five, six,
seven, or eight bits per character. In all cases, the data must be right justified, with the unused bits
being ignored, except in the case of five bits per character. When five bits per character are
selected, the data may be formatted before being written to the transmit buffer. This allows trans-
mission of one to five bits per character ( Table on page 94).
An additional bit, carrying parity information, is automatically appended to every transmitted
character by setting bit D0 of WR4 to 1. This bit is sent in addition to the number of bits specified
in WR4 or by the data format. The parity sense is selected by bit D1 of WR4. Parity is not nor-
mally used in SDLC mode as the overhead of parity is unnecessary due to the availability of the
CRC.
The SCC transmits address and control fields as normal data and does not automatically send any
address or control information. The value programmed into WR6 is used by the receiver to com-
pare the address of the received frame (if address search mode is enabled), but WR6 is not used by
the transmitter. Therefore, the address is written to the transmitter as the first byte of data in the
frame.
The information field can be any number of characters long. On the NMOS/CMOS version, the
transmitter can interrupt the CPU when the transmit buffer is empty. On the ESCC, the transmitter
can interrupt the CPU when the entry location of the Transmit FIFO is empty or when the Trans-
mit FIFO is completely empty. Also, the NMOS/CMOS version can issue a DMA request when
the transmit buffer is empty, while the ESCC can issue a DMA request when the entry location of
the Transmit FIFO is empty or when the Transmit FIFO is completely empty. This allows the
ESCC user to optimize the response to the application requirements. Since the ESCC has a four
byte Transmit FIFO buffer, the Transmit Buffer Empty (TBE) bit (D2 of RR0) will become set
when the entry location of the Transmit FIFO becomes empty. The TBE bit will reset when a byte
of data is loaded into the entry location of the Transmit FIFO. For more details on this subject, see
Transmit Interrupts and Transmit Buffer Empty Bit on page 49.
The character length may be changed on the fly, but the desired length must be selected before the
character is loaded into the Transmit Shift register from the transmit data FIFO. The easiest way to
ensure this is to write to WR5 to change the character length before writing the data to the transmit
buffer. Note that although the character can be any length, most protocols specify the address/con-
trol field as 8-bit fields. The SCC receiver checks the address field as 8-bit, if address search mode
is enabled.