Zilog Z80230 - Manual (Page 12)

SCC/ESCC
User Manual
UM010903-0515 General Description
5
– Receive FIFO automatically unlocked for special receive interrupts when using
the SDLC status FIFO
• Delayed bus latching for easier microprocessor interface
• New programmable features added with Write Register 7' (WR seven prime)
• Write registers 3, 4, 5 and 10 are now readable
• Read register 0 latched during access
• DPLL counter output available as jitter-free transmitter clock source
• Enhanced /DTR, /RTS deactivation timing
Block Diagram
Figure on page 6 displays the block diagram of the SCC. Note that the depth of the FIFO differs
depending on the version. The 10X19 SDLC Frame Status FIFO is not available on the NMOS
version of the SCC. Detailed internal signal path will be discussed in Data Communication Modes
on page 88.