Zilog Z80230 - Manual (Page 228)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
221
If you are familiar with the Z80 ® CPU design, the same interfacing logic applies to the Z180 and I/
O interface (see Figure ). This circuit generates /IORD (Read) or IORD (Write) for peripherals
from inputs /IORQ, /RD, and /WR. The address decodes the Chip Select signal.
If you have Z80 peripherals, the decoder logic decodes only from addresses (does not have /
IORQ).
The Z180 signals /IORQ, /RD, and /WR are active at about the same time (Parameters #9, 22, 28).
However, most of the Z80 peripherals require /CE to /RD or /WR setup time.
Since the Z180 occupies 64 bytes of I/O addressing space for system control and on-chip peripher-
als, there are no overlapping I/O addresses for off-chip peripherals. In this design, leave the area as
default or assign on-chip registers at I/O address
0000h
to
003Fh
.
16 tDRH Data Read Hold Time 0 ns
21 tWDS Clock High to Data Float Delay 60 ns
22 tWRD1 Clock High to /WR Low 50 ns
23 tWDD Clock Low to Write Data Delay 60 ns
24 tWDS Write Data Setup to /WR Low 15 ns
25 tWRD2 Clock Low to /WR High 50 ns
26a tWRP /WR Pulse Width (I/O Write) 210 ns
27 tWDH /WR High to Data Hold Time 10 ns
28 tIOD1 Clock High to /IORQ Low IOC=0 55 ns
29 tIOD2 Clock Low to /IORQ High 50 ns
Note: Parameter numbers in this table are the numbers in the Z180 technical manual.
Z8018010 Timing Parameters for I/O Cycle (Worst Case) (Continued)
Sr. No Symbol Parameter Min Max Units
Note: