Zilog Z80230 User Manual
Page 124
SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
117
The SCC sets the Tx Underrun/EOM latch when the CRC or abort is loaded into the shift register
for transmission. This event can cause an interrupt, and the status of the Tx Underrun/EOM latch
can be read in RR0.
Resetting the Tx Underrun/EOM latch is done by the processor via the command encoded in bits
D7 and D6 of WR0. On the 85X30, this also can be accomplished by setting WR7' bit D1 for Auto
Tx Underrun/EOM Latch Reset mode enabled. For correct transmission of the CRC at the end of a
frame, this command must be issued after the first character is written to the SCC but before the
transmitter underruns after the last character written to the SCC. The command is usually issued
immediately after the first character is written to the SCC so that the abort or CRC is sent if an
underrun occurs inadvertently. The Abort/Flag on Underrun bit (D2) in WR10 is usually set to 1 at
the same time as the Tx Underrun/EOM bit is reset so that an abort is sent if the transmitter under-
runs. The bit is then set to 0 near the end of the frame to allow the correct transmission of the CRC.
In this paragraph the term “completely sent” means shifted out of the Transmit Shift register, not
shifted out of the zero inserter, which is an additional five bit times of delay. In SDLC mode, if the
transmitter is disabled during transmission of a character, that character will be “completely sent.”
This applies to both data and flags. However, if the transmitter is disabled during the transmission
of the CRC, the 16-bit transmission will be completed, but the remaining bits are from the Flag
register rather than the remainder of the CRC.
The initialization sequence for the transmitter in SDLC mode is:
1. WR4 selects the mode.
2. WR10 modifies it if necessary.
3. WR7 programs the flag.
4. WR3 and WR5 selects the various options.
At this point the other registers should be initialized as necessary. When all of this is complete, the
transmitter may be enabled by setting bit D3 of WR5 to 1. Now that the transmitter is enabled, the
CRC generator may be initialized by issuing the Reset Tx CRC Generator command in WR0.
ESCC Action Taken on Tx Underrun
Tx Underrun /
EOM Latch Bit
Abort/
Flag
Action taken by
ESCC upon
transmit underrun
0
0
Sends CRC followed
by flag
0
1
Sends abort followed
by flag
1
x
Sends flag