Document Outline

• ATCA-8310
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Introduction
  • 1.1 Features
  • 1.2 Standard Compliances
  • 1.3 Mechanical Data
  • 1.4 Product Identification
  • 1.5 Ordering Information
• Hardware Preparation and Installation
  • 2.1 Unpacking and Inspecting the Blade
  • 2.2 Environmental and Power Requirements
    • 2.2.1 Environmental Requirements
    • 2.2.2 Power Requirements
  • 2.3 Blade Layout
  • 2.4 Switch Settings
  • 2.5 Installing and Removing the Blade
    • 2.5.1 Installing the Blade
    • 2.5.2 Removing the Blade
• Controls, Indicators, and Connectors
  • 3.1 Face Plate
    • 3.1.1 LEDs
    • 3.1.2 Keys
    • 3.1.3 Connectors
  • 3.2 Onboard Connectors
  • 3.3 ATCA Backplane Connectors
  • 3.4 Connector Pin Definitions
    • 3.4.1 Zone 2
    • 3.4.2 Zone 3
    • 3.4.3 DMC Connector
    • 3.4.4 VGA Connector
    • 3.4.5 Ethernet Connector
    • 3.4.6 Serial Connector
    • 3.4.7 USB Connector
• Functional Description
  • 4.1 Block Diagram
  • 4.2 Service and Packet Processor (SPP)
    • 4.2.1 Memory Interface
      • 4.2.1.1 Local Bus
      • 4.2.1.2 SPI Interface
      • 4.2.1.3 P4080 USB and Mass Storage
      • 4.2.1.4 P4080 Serdes Configuration
      • 4.2.1.5 Freescale P4080 PCI-Express
      • 4.2.1.6 Freescale P4080 Serial Rapid IO SRIO
      • 4.2.1.7 Freescale P4080 Ethernet
      • 4.2.1.8 Dual UART
      • 4.2.1.9 I2C Interface
  • 4.3 General Purpose Processor (GPP)
    • 4.3.1 Intel x86 CPU
      • 4.3.1.1 Thermal Monitor
      • 4.3.1.2 Chipset Connection
      • 4.3.1.3 GPP System Memory
    • 4.3.2 Mobile Intel 5 Series Chipset
      • 4.3.2.1 PCI Express Interface of the Ibex-Peak
      • 4.3.2.2 Ibex-Peak Display
      • 4.3.2.3 Ibex-Peak LPC
      • 4.3.2.4 Ibex-Peak SPI
      • 4.3.2.5 Ibex-Peak SATA
      • 4.3.2.6 Ibex-Peak USB
      • 4.3.2.7 GPP System Management Bus (SMBus)
      • 4.3.2.8 Ibex-Peak RTC
    • 4.3.3 GPP Ethernet Connectivity
      • 4.3.3.1 Dual Gigabit Ethernet Controller Intel 82576
      • 4.3.3.2 Single Gigabit Ethernet Controller 82574
  • 4.4 DSP Farm
    • 4.4.1 Digital Signal Processor
      • 4.4.1.1 DSP Configuration
      • 4.4.1.2 Boot Mode Selection
      • 4.4.1.3 EMAC Boot Mode
    • 4.4.2 DSP Memory
    • 4.4.3 DSP TSIP Interface
    • 4.4.4 SRIO Interface
    • 4.4.5 RGMII Interface
    • 4.4.6 DSP-FPGA
    • 4.4.7 Module IPMC Interface
    • 4.4.8 Configuration Identifier
      • 4.4.8.1 Base Board and Module Slot Identifier
      • 4.4.8.2 Module Functional Identifier
      • 4.4.8.3 DSP Mezzanine Card Identifier
  • 4.5 Ethernet Network (ETH)
    • 4.5.1 Ethernet Network Overview
    • 4.5.2 ETH Switch Unit
      • 4.5.2.1 Ethernet Switch Device
      • 4.5.2.2 Switch management
      • 4.5.2.3 PHY connection
    • 4.5.3 ATCA Fabric Interface
    • 4.5.4 ATCA Base Interface and SOL
      • 4.5.4.1 Serial over LAN
  • 4.6 Timing Synchronization (TS)
    • 4.6.1 Oscillator
  • 4.7 Glue Logic FPGA
    • 4.7.1 SPI System Overview
  • 4.8 IPMC
  • 4.9 Reset Structure
    • 4.9.1 Reset Types
      • 4.9.1.1 GPP-Reset
      • 4.9.1.2 SPP-Reset
      • 4.9.1.3 Reset Sources
      • 4.9.1.4 RTM Reset Behavior
• BIOS
  • 5.1 BIOS Considerations
    • 5.1.1 Shared Memory Parameters
      • 5.1.1.1 clid Parameter
      • 5.1.1.2 btorder Parameter
      • 5.1.1.3 bootwd Parameter
    • 5.1.2 Boot Options
    • 5.1.3 Redirection of Console I/O
    • 5.1.4 Board Information display
  • 5.2 BIOS Operation
    • 5.2.1 POST
    • 5.2.2 Boot Process
    • 5.2.3 Initiating Setup
  • 5.3 Setup Utility
    • 5.3.1 Main Menu
      • 5.3.1.1 Platform Information
    • 5.3.2 Advanced Menu
      • 5.3.2.1 PCI Subsystem Sub-menu
      • 5.3.2.2 ACPI Settings
      • 5.3.2.3 Trusted Computing
      • 5.3.2.4 S5 RTC Wake Settings
      • 5.3.2.5 CPU Configuration
      • 5.3.2.6 ME Configuration
      • 5.3.2.7 Thermal Configuration
      • 5.3.2.8 Port 80h
      • 5.3.2.9 TDT Configurations
      • 5.3.2.10 USB Configurations
      • 5.3.2.11 AMT Configuration
      • 5.3.2.12 Super IO Configuration
      • 5.3.2.13 Serial Port Console Redirection
      • 5.3.2.14 Network Stack
    • 5.3.3 Chipset Menu
      • 5.3.3.1 North Bridge Configuration
      • 5.3.3.2 South Bridge Configuration
    • 5.3.4 Boot Menu
    • 5.3.5 Security Menu
    • 5.3.6 Save Menu
  • 5.4 Status Codes
    • 5.4.1 Status Code Ranges
    • 5.4.2 SEC Progress
    • 5.4.3 SEC Errors
    • 5.4.4 PEI Progress
    • 5.4.5 PEI Errors
    • 5.4.6 DXE Progress
    • 5.4.7 DXE Errors
    • 5.4.8 CPU Exceptions
    • 5.4.9 ACPI/ASL Checkpoints
    • 5.4.10 OEM-Reserved Checkpoint Ranges
• U-Boot
  • 6.1 Overview
  • 6.2 U-Boot
    • 6.2.1 User Interface
      • 6.2.1.1 Memory Map
      • 6.2.1.2 Environment Variables
      • 6.2.1.3 Network interfaces
      • 6.2.1.4 GPP Control
      • 6.2.1.5 Firmware Update
      • 6.2.1.6 FPGA/Logic Operations
      • 6.2.1.7 IPMI Interface
      • 6.2.1.8 Application Boot
      • 6.2.1.9 Default Boot Sequences
      • 6.2.1.10 Broadcom Switch Configuration
      • 6.2.1.11 Memory Initialization
      • 6.2.1.12 SRIO Initialization
      • 6.2.1.13 Miscellaneous Commands and Features
      • 6.2.1.14 Power-on Self Test (POST)
      • 6.2.1.15 Troubleshooting
• Intelligent Peripheral Management Controller
  • 7.1 IPMC Overview
  • 7.2 Functional Overview
  • 7.3 Firmware Architecture
  • 7.4 HPM.1 Firmware Upgrade and Crisis Recovery
  • 7.5 Sensors
    • 7.5.1 Firmware Progress, OS Boot, and Boot Error Sensor
    • 7.5.2 Boot Bank Supervision Sensor
    • 7.5.3 POST Results Sensor
    • 7.5.4 Power Good Sensor
    • 7.5.5 SW Progress Sensors
    • 7.5.6 Power Interface Sensors
    • 7.5.7 Reset Cause Sensor
    • 7.5.8 Presence Sensors
    • 7.5.9 Voltage and Temperature Sensors
  • 7.6 Sensor Data Records
  • 7.7 POST
  • 7.8 FRU Inventory
    • 7.8.1 MAC Address FRU OEM Records
  • 7.9 Reset Domains and FRU Activation/Deactivation
  • 7.10 U-Boot Boot Configuration Parameters
  • 7.11 Asynchronous Event Notification
  • 7.12 Serial Line Selection
  • 7.13 Built-in Terminal Server
    • 7.13.1 Evaluating the Version of the Telnet Server Firmware
    • 7.13.2 Establishing a Telnet Session
  • 7.14 Fail Safe Logic and Watchdog Support
    • 7.14.1 SPP BMC Watchdog
    • 7.14.2 SPP FPGA Watchdog
  • 7.15 Payload Interface
  • 7.16 Payload Boot Bank Selection
  • 7.17 Settable Graceful Shutdown Timeout
  • 7.18 FPGA Health Check
  • 7.19 GPP THERMTRIP
  • 7.20 Local System Event Log (SEL)
  • 7.21 IPMI Hardware Watchdog
  • 7.22 Artesyn OEM Command Set
    • 7.22.1 Set Serial Output Command
    • 7.22.2 Get Serial Output Command
    • 7.22.3 Set Feature Configuration
    • 7.22.4 Get Feature Configuration
    • 7.22.5 Send SW Progress Data
• CPLD and FPGA
  • 8.1 Power-up CPLD
    • 8.1.1 Power-up CPLD Architectural Overview
      • 8.1.1.1 Unit Description
    • 8.1.2 CPLD Registers
      • 8.1.2.1 CPLD Register Overview
      • 8.1.2.2 CPLD Registers Detailed Description
    • 8.1.3 Reset Structure
    • 8.1.4 Clocking Scheme
    • 8.1.5 Logic Blocks
      • 8.1.5.1 IPMC Watchdog
      • 8.1.5.2 IPMC IRQ
      • 8.1.5.3 FPGA Configuration Logic
      • 8.1.5.4 CPLD Serial Redirection
      • 8.1.5.5 IPMC SPI Interfaces
      • 8.1.5.6 FPGA SPI Interface
  • 8.2 Glue Logic FPGA
    • 8.2.1 Glue Logic FPGA Architectural Overview
      • 8.2.1.1 Unit Description
    • 8.2.2 Registers
      • 8.2.2.1 Register Decoding
      • 8.2.2.2 Glue Logic FPGA Register Mapping
      • 8.2.2.3 Glue Logic FPGA Register Overview
    • 8.2.3 Logic Blocks
      • 8.2.3.1 Telecom Clocking
      • 8.2.3.2 Asynchronous Receiver Transmitter
      • 8.2.3.3 Super IO Module
      • 8.2.3.4 GPP Reset Controller
      • 8.2.3.5 Watchdog Controller
      • 8.2.3.6 GPP Interrupt Mapping Unit
      • 8.2.3.7 SPP Interrupt Routing
      • 8.2.3.8 Hardware Protection
      • 8.2.3.9 Glue Logic FPGA Configuration Supervision
      • 8.2.3.10 Glue Logic FPGA Dual Configuration
      • 8.2.3.11 Communication between SPP, GPP and IPMC
      • 8.2.3.12 SPP Failure Detection
      • 8.2.3.13 SPP Persistent memory
      • 8.2.3.14 SPI Interfaces DCM baseboard, DMC1, DMC2 and ARTM
      • 8.2.3.15 Serial Redirection
      • 8.2.3.16 Reset Domain Control
      • 8.2.3.17 Miscellaneous
  • 8.3 DSP FPGA
    • 8.3.1 DSP FPGA Architectural Overview
  • 8.4 DSP FPGA HW/SW interfaces
    • 8.4.1 DSP FPGA Address map Overview
    • 8.4.2 DSP FPGA Registers Detailed Description
      • 8.4.2.1 SerDes Client Interface (8bit each) (SerDesClientIf)
      • 8.4.2.2 TSIP Interface Test Pattern Generator Block (TstPatGenBlk)
      • 8.4.2.3 TSIP Interface Test Pattern Comparator Block ( TstPatCmpBlk)
      • 8.4.2.4 TSIP to Serializer Converter Block (Tsip2SerBlk)
      • 8.4.2.5 Deserializer to TSIP Allocater Block (Des2TsipBlk)
      • 8.4.2.6 DSP Reset and NMI Control Block (DspResNmiCtrlBlk)
      • 8.4.2.7 DSP Status and Interrupt Block (DspStaIntBlk)
      • 8.4.2.8 DMC Power Supply Control Block (DmcPwrCtrlBlk)
      • 8.4.2.9 General Registers (GnrlRegs)
      • 8.4.2.10 Configuration Prom Update Registers (CfgPrmUpd)
      • 8.4.2.11 General Test Registers (GenTestRegs)
      • 8.4.2.12 I2C interface to Dsps (I2CIfToDsp)
      • 8.4.2.13 MDIO interface to Phy (MdioIfToPhy)
    • 8.4.3 Logic Blocks
      • 8.4.3.1 Logic blocks Overview
      • 8.4.3.2 Transmission principle between TSIP and SERDES
      • 8.4.3.3 Setting up SERDES links
      • 8.4.3.4 Pseudo Random Generator and Comparator (PRGC)
      • 8.4.3.5 DSP Status and Interrupt Interface (DSI)
      • 8.4.3.6 Base ID and Sub module ID Register (BSID)
      • 8.4.3.7 Debug LEDs
• A Replacing the Battery
  • A.1 Replacing the Battery
• B Related Documentation
  • B.1 Artesyn Embedded Technologies - Embedded Computing Documentation
• Safety Notes
  • EMC
  • Installation
  • Operation
  • Switch Settings
  • Battery
  • Environment
• Sicherheitshinweise
  • EMV
  • Installation
  • Betrieb
  • Schaltereinstellungen
  • Batterie
  • Umweltschutz