Csu timing, Csu timing -13 – Verilink DIU 2130 (880-503297-001) Product Manual User Manual

Page 93

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DIU/DIM Details

Verilink

7-13

CSU Timing

When a CSU is used with DIUs, the associated DIUs must be timed
from a reference clock source. The CSU synchronizes itself with the
DIUs by deriving two separate timing signals (transmit and receive
clocks) from the reference clock source. It sends these signals to
the DIUs over the assigned data bus.

To support various T1 network applications, the Access System
2000 offers several operator-selectable system timing options.
These options are:

Through timing

Internal timing

Network timing

Equipment timing

External timing

Data equipment timing (DTE)

In all of the above timing modes, the transmit and receive clocks
sent by the CSU to the DIUs over the assigned data bus are 1.544
MHz clocks. The DIUs divide these clocks down to the proper rates
before sending them to the customer data equipment.

Through Timing

Through timing is commonly used in drop-and-insert mode. Signal
clocking through the CSU occurs as described above in each
direction. Also, the CSU sends the transmit and receive clocks to
the DIUs. These are used to clock data from the T1 multiplexers of
the CSU to the associated DIUs, and from the DIUs to the CSU.

For through timing with drop-and-insert toward the network, the
receive DIU clock is derived from the incoming network signal and
applied to the DIUs via Data Bus A. (Figure 7-13). The DIU transmit
clock and the CSU transmit clock to the network are similarly
derived from the incoming signal from the equipment. The
transmit and receive clocks are applied to the DIUs via Data Bus A.

Loop Timing

In loop timing, the reference clocks that synchronize the CSU with
the associated DIUs are derived from a DS1 signal received by the
CSU. These clocks can be derived from either the incoming network
signal (network timing) or the equipment signal (equipment
timing).

Network Timing

Typical applications of network timing in the T1 multiplexer and
the drop-and-insert CSU modes are shown in these figures:

Figure 7-15

Figure 7-16

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