Interrupt line, Register: 0x3c – Avago Technologies LSI53C1030 User Manual
Page 101
PCI Configuration Space Register Description
4-15
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Capabilities Pointer
[7:0]
This register indicates the location of the first extended
capabilities register in PCI Configuration Space. The
value of this register varies according to system configu-
ration.
Register: 0x35–0x37
Reserved
Reserved
[23:0]
This register is reserved.
Register: 0x38–0x3B
Reserved
Reserved
[31:0]
This register is reserved.
Register: 0x3C
Interrupt Line
Read/Write
Interrupt Line
[7:0]
This register communicates interrupt line routing informa-
tion. Power-On-Self-Test (POST) software writes the rout-
ing information into this register as it configures the
system. This register indicates the system interrupt con-
troller input to which this PCI function’s interrupt pin con-
nects. System architecture determines the values in this
register.
23
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
Interrupt Line
0
0
0
0
0
0
0
0