Avago Technologies LSI53C1030 - Manual (Page 128)

5-4 Specifications
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.2 LVD Receiver
V
CM
+
−
+
+
+
−
−
− V
I
2
V
I
2
Table 5.5 A_DIFFSENS and B_DIFFSENS SCSI Signals
Symbol Parameter Min Max Unit Test Conditions
V
IH
HVD sense voltage 2.4 3.6 V Note 1
V
S
LVD sense voltage 0.7 1.9 V Note 1
V
IL
SE sense voltage V
SS
−
0.35 0.5 V Note 1
I
OZ
3-state leakage
−
10 10
µ
A V
PIN
= 0 V, 3.6 V
1. V
IH
, V
IL
, and V
s
are specified in the SPI-4 draft specification.
Table 5.6 Input Capacitance
Symbol Parameter Min Max Unit Test Conditions
C
I
Input capacitance of input pads – 7 pF Guaranteed by design
C
IO
Input capacitance of I/O pads – 15 pF Guaranteed by design
C
PCI
Input capacitance of PCI pads – 8 pF Guaranteed by design
C
LVD
Input capacitance of LVD pads – 8 pF 6.5 pF pad
1.5 pF package