Avago Technologies LSI53C1030 - Manual (Page 137)

External Memory Timing Diagrams 5-13
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Table 5.17 and Figure 5.9 provide the timing information for NVSRAM
write accesses.
Table 5.17 NVSRAM Write Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to FLSHALE/ HIGH 25 – ns
t
12
Address hold from FLSHALE/ HIGH 25 – ns
t
13
FLSHALE/ pulse width 25 – ns
t
20
Data setup to BWE0/ LOW 40 – ns
t
21
Data hold from BWE0/ HIGH 30 – ns
t
22
BWE0/ pulse width 20 – ns
t
23
Address setup to BWE0/ LOW 75 – ns
t
24
RAMCE/ LOW to BWE0/ HIGH 60 – ns
t
25
RAMCE/ LOW to BWE0/ LOW 25 – ns
t
26
BWE0/ HIGH to RAMCE/ HIGH 25 – ns
t
27
RAMCE/ pulse width 100 – ns