Avago Technologies LSI53C1030 - Manual (Page 138)

5-14 Specifications
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.9 NVSRAM Write Cycle
Figure 5.9 NVSRAM Write Cycle (Cont.)
MAD Bus
(Driven by LSI53C1030)
High Order Address
Middle Order
Address
Low Order
Address
FLSHALE1/
(Driven by LSI53C1030)
FLSHALE0/
(Driven by LSI53C1030)
RAMCE/
(Driven by LSI53C1030)
MOE/
(Driven by LSI53C1030)
BWE0/
(Driven by LSI53C1030)
t
13
t
11
t
12
t
24
t
25
Write
Data
Valid
t
23
t
20
t
27
MAD Bus
(Driven by LSI53C1030)
FLSHALE1/
(Driven by LSI53C1030)
FLSHALE0/
(Driven by LSI53C1030)
RAMCE/
(Driven by LSI53C1030)
MOE/
(Driven by LSI53C1030)
BWE0/
(Driven by LSI53C1030)
t
24
t
25
t
21
Valid Write Data
t
20
t
23
t
22
t
26
t
27