Avago Technologies LSI53C1030 - Manual (Page 63)

Signal Organization 3-3
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 3.1 LSI53C1030 Functional Signal Grouping
MAD[15:0]
FLSHCE/
FLSHALE[1:0]/
BWE[1:0]/
ADSC/
SerialDATA
CLK
RST/
AD[63:0]
C_BE[7:0]/
PAR
PAR64
ACK64/
REQ64/
FRAME/
IRDY/
TRDY/
DEVSEL/
STOP/
IDSEL
REQ/
GNT/
PERR/
SERR/
INTA/
INTB/
ALT_INTA/
ALT_INTB/
SCLK
A_SD[15:0]
A_SDP[1:0]
A_SCD
±
A_SIO
±
A_SMSG
±
A_SREQ
±
A_SBSY
±
A_SATN
±
A_SRST
±
A_SSEL
±
B_SDP[1:0]
B_SCD
±
B_SIO
±
B_SMSG
±
B_SREQ
±
B_SBSY
±
B_SATN
±
B_SRST
B_SSEL
±
B_SD[15:0]
±
B_DIFFSENS
A_DIFFSENS
LSI53C1030
SCSI
Function
A
SCSI
Function
B
Test
Interface
SCSI Bus
Interface
System
Address
and Data
Interface
Control
Arbitration
Error
Reporting
Interrupt
Memory
Interface
Interface
A_SCTRL/
B_SCTRL/
A_SACK
±
B_SACK
±
GPIO
Interface
MADP[1:0]
MCLK
ADV/
RAMCE/
SerialCLK
MOE/
TRACEPKT[7:0]
PIPESTAT[2:0]
TRACECLK
TRACESYNC
TCK_ICE
TMS_ICE
TDI_ICE
TRST_ICE/
RTCK_ICE
TCK_CHIP
TST_RST/
TMS_CHIP
TDI_CHIP
TDO_CHIP
IDDTN
SCANEN
GPIO[7:0]
A_LED/
B_LED/
HB_LED/
A_RBIAS
B_RBIAS
PCI Bus
PVT1
TDO_ICE
PCI Bus
Related Signals
CLKMODE_0
CLKMODE_1
DIS_SCSI_FSN/
TESTHCLK
TESTACLK
TESTCLKEN
SCANMODE
TN
DIS_PCI_FSN/
ZCR_EN/
IOPD_GNT/
ZCR Interface
PVT2