Avago Technologies LSI53C1030 - Manual (Page 80)

3-20 Signal Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
3.9 Power and Ground Pins
Table 3.19 describes the Power and Ground signals.
Table 3.19 Power and Ground Pins
Signal Name BGA Position Type Strength Description
VDD_IO A1, A2, A6, A10, A14, A18, A22, A26,
C7, C11, C15, C19, C23, D3, E26, F1,
G24, H3, J26, K1, L24, M3, N26, P1,
R24, T3, U26, V1, W24, Y3, AA26,
AB1, AC24, AD4, AD8, AD12, AD16,
AD20, AE26, AF1, AF5, AF9, AF13,
AF17, AF21, AF25 P N/A VDD_IO provides power
for the PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local
memory interface
drivers/receivers, and
other I/O pins.
VSS_IO A5, A9, A13, A17, A21, A25, B1, B26,
C4, C8, C12, C16, C20, D24, E1, F26,
G3, H24, J1, K26, L3, L11-L16,
M11-M16, M24, N1, N11-N16,
P11-P16, P26, R3, R11-R16,
T11-T16, T24, U1, V26, W3, Y24,
AA1, AB26, AC3, AD7, AD11, AD15,
AD19, AD23, AE1, AF2, AF6, AF10,
AF14, AF18, AF22, AF26 G N/A VSS_IO provides ground
for the PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local
memory interface
drivers/receivers, and
other I/O pins.
VDDA
1
AB21, C1 P N/A VDDA provides the analog
circuit power for the PLL
circuit.
VSSA
1
AD24, H5 G N/A VSSA provides the analog
circuit ground for the PLL
circuit.
VDDC D2, D6, D15, E19, J22, M22, N2, AC7,
AD3, AD25, AE3, AE24, AF15 P N/A VDDC provides power for
the core logic.
VSSC B4, C14, C21, C26, F25, G4, L22, P2,
AB5, AB7, AB8, AB23, AB24, AD14 G N/A VSSC provides ground for
the core logic.
PCI5VBIAS M23, W25, Y22, AB22, AC10, AD9,
AD18, AE6, AF12 I N/A Connects the PCI 5V
Tolerant pins to 5 V in a
5 V system or to 3.3 V in a
3.3 V system.
NC AC9 – N/A No Connect.
1. To reduce signal noise that can affect FSN functionality, place a ferrite bead in series with the VDDA
and VSSA pins. LSI Logic recommends a bead with a rating of 150
Ω
at 100 MHz.