Avago Technologies LSI53C1030 - Manual (Page 166)

IX-12 Index
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
transfer width 2-18
transfers
information units 2-21
packetized 2-21
TRDY/ 3-6 , 5-5
TRST_ICE/ 2-30 , 3-17 , 3-25 , 5-6
TST_RST/ 3-17 , 3-25 , 5-6
TTL interrupt bit 4-32
U
Ultra160 SCSI
DT clocking 1-2 , 2-18
parallel protocol request 2-22
PPR 2-22
Ultra320 SCSI 1-5 , 1-7
benefits 1-7
bus training 1-10
channel modules 2-2
core 2-6
CRC 2-22
domain validation 2-22
DT clocking 1-2 , 2-18
features 1-2 , 2-18 , 2-19
functional description 2-18
information unit 2-21
ISI 1-7 , 2-19
paced transfers 2-19
packetized transfers 2-21
parallel protocol request 2-18 , 2-22
PPR 2-18
precompensation 2-20
QAS 2-21
quick arbitration and selection 2-21
skew compensation 1-2 , 1-7 , 1-10 , 2-22
unexpected split completion bit 4-27
V
VDD_CORE 5-3
VDD_IO 3-20 , 5-2
VDDA 3-20
VDDC 3-20 , 5-2
vendor ID register 4-3
version bit 4-18
voltage
analog 5-2
common mode 5-3
core 5-2 , 5-3
feed-through protection 1-13
I/O 5-2
input 5-2
supply 5-2
VSS_IO 3-20
VSSA 3-20
VSSC 3-20
W
write and invalidate enable bit 4-4
write flow 2-18
write I/O key 4-31 , 4-34
write journaling 2-26
write sequence register 4-30 , 4-31 , 4-34
Z
ZCR 2-28 , 2-29 , 3-16
ZCR_EN/ 2-28 , 3-16 , 3-25 , 5-6
zero channel RAID 2-28 , 2-29 , 3-16