Avago Technologies LSI53C1030 - Manual (Page 136)

5-12 Specifications
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.8 NVSRAM Read Cycle
Figure 5.8 NVSRAM Read Cycle (Cont.)
Data Driven by NVSRAM)
MAD Bus
(Addr Driven by LSI53C1030; High Order Address
Middle Order
Address
FLSHALE1/
(Driven by LSI53C1030)
FLSHALE0/
(Driven by LSI53C1030)
RAMCE/
(Driven by LSI53C1030)
MOE/
(Driven by LSI53C1030)
BWE0/
(Driven by LSI53C1030)
t
3
t
1
t
2
t
4
t
5
t
6
Low Order
Address
Data Driven by NVSRAM)
MAD Bus
(Addr Driven by LSI53C1030;
FLSHALE1/
(Driven by LSI53C1030)
FLSHALE0/
(Driven by LSI53C1030)
RAMCE/
(Driven by LSI53C1030)
MOE/
(Driven by LSI53C1030)
BWE0/
(Driven by LSI53C1030)
t
4
t
9
t
5
Valid
t
6
t
8
t
7
Read Data