Avago Technologies LSI53C1030 - Manual (Page 11)

Contents xi
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figures
1.1 Typical LSI53C1030 Board Application 1-3
1.2 Typical LSI53C1030 System Application 1-4
2.1 LSI53C1030 Block Diagram 2-3
2.2 Paced Transfer Example 2-20
2.3 Example of Precompensation 2-21
2.4 Flash ROM Block Diagram 2-25
2.5 NVSRAM Diagram 2-27
2.6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R 2-29
3.1 LSI53C1030 Functional Signal Grouping 3-3
5.1 LVD Driver 5-3
5.2 LVD Receiver 5-4
5.3 Rise and Fall Time Test Condition 5-8
5.4 SCSI Input Filtering 5-9
5.5 External Clock 5-10
5.6 Reset Input 5-10
5.7 Interrupt Output 5-11
5.8 NVSRAM Read Cycle 5-12
5.8 NVSRAM Read Cycle (Cont.) 5-12
5.9 NVSRAM Write Cycle 5-14
5.9 NVSRAM Write Cycle (Cont.) 5-14
5.10 Flash ROM Read Cycle 5-15
5.10 Flash ROM Read Cycle (Cont.) 5-16
5.11 Flash ROM Write Cycle 5-17
5.11 Flash ROM Write Cycle (Cont.) 5-17
5.12 LSI53C1030 456-Pin BGA Top View 5-20
5.12 LSI53C1030 456-Pin BGA Top View (Cont.) 5-21
5.13 456-Pin EPBGA (KY) Mechanical Drawing 5-26