Avago Technologies LSI53C1030 - Manual (Page 18)

1-2 Introduction
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
The LSI53C1030 is pin compatible with the LSI53C1010R PCI to Dual
Channel Ultra160 SCSI Multifunction Controller to provide an easy and
safe migration path to Ultra320 SCSI. The LSI53C1030 supports up to a
64-bit, 133 MHz PCI-X bus. The Ultra320 SCSI features for the
LSI53C1030 include: double transition (DT) clocking, packetized protocol,
paced transfers, quick arbitrate and select (QAS), skew compensation,
intersymbol interference (ISI) compensation, cyclic redundancy check
(CRC), and domain validation technology. These features comply with
the American National Standard Institute (ANSI) T10 SCSI Parallel
Interface-4 (SPI-4) draft specification.
DT clocking enables the LSI53C1030 to achieve data transfer rates of up
to 320 megabytes per second (Mbytes/s) on each SCSI channel, for a
total bandwidth of 640 Mbytes/s on both SCSI channels. Packetized
protocol increases data transfer capabilities with SCSI information units.
QAS minimizes SCSI bus latency by allowing the bus to directly enter the
arbitration/selection bus phase after a SCSI disconnect and skip the bus
free phase. Skew compensation permits the LSI53C1030 to adjust for
cable and bus skew on a per-device basis. Paced transfers enable high
speed data transfers during DT data phases by using the REQ/ACK
transition as a free running data clock. Precompensation enables the
LSI53C1030 to adjust the signal drive strength to compensate for the
charge present on the cable. CRC improves the SCSI data transmission
integrity through enhanced detection of communication errors.
SureLINK™ Domain Validation detects the SCSI bus configuration and
adjusts the SCSI transfer rate to optimize bus interoperability and SCSI
data transfer rates. SureLINK Domain Validation provides three levels of
domain validation, assuring robust system operation.
The LSI53C1030 supports a local memory bus, which supports a
standard serial EEPROM and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1030 supports programming of local Flash
ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030
board application connected to external ROM memory.