Avago Technologies LSI53C1030 - Manual (Page 14)

xiv Contents
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
4.8 PCI Memory [1] Address Map 4-29
4.9 Interrupt Signal Routing 4-36
5.1 Absolute Maximum Stress Ratings 5-2
5.2 Operating Conditions 5-2
5.3 LVD Driver SCSI Signals— SACK
±
, SATN
±
, SBSY
±
,
SCD
±
, SD[15:0]
±
, SDP[1:0]
±
, SIO
±
, SMSG
±
, SREQ
±
,
SRST
±
, SSEL
±
5-3
5.4 LVD Receiver SCSI Signals— SACK
±
, SATN
±
, SBSY
±
,
SCD
±
, SD[15:0]
±
, SDP[1:0]
±
, SIO
±
, SMSG
±
, SREQ
±
,
SRST
±
, SSEL
±
5-3
5.5 A_DIFFSENS and B_DIFFSENS SCSI Signals 5-4
5.6 Input Capacitance 5-4
5.7 8 mA Bidirectional Signals — GPIO[7:0], MAD[15:0],
MADP[1:0], SerialDATA
5-5
5.8 8 mA PCI Bidirectional Signals — ACK64/, AD[63:0],
C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, PAR, PAR64,
PERR/, REQ64/, SERR/, STOP/, TRDY/
5-5
5.9 Input Signals — CLK, CLKMODE_0, CLKMODE_1,
DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL,
IOPD_GNT/, PVT1, PVT2, SCANEN, SCANMODE,
SCLK, TCK_CHIP, TCK_ICE, TESTACLK, TESTCLKEN,
TESTHCLK, TDI_CHIP, TDI_ICE, TMS_CHIP, TMS_ICE,
TN, TRST_ICE/, TST_RST/, ZCR_EN/
5-6
5.10 8 mA Output Signals — ADSC/, ADV/, ALT_INTA/,
ALT_INTB/, BWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/,
INTB/, MCLK, MOE/, PIPESTAT[2:0], RAMCE/, REQ/,
RTCK_ICE, SerialCLK, SERR/, TDO_CHIP, TDO_ICE,
TRACECLK, TRACEPKT[7:0], TRACESYNC
5-6
5.11 12 mA Output Signals — A_LED/, B_LED/, HB_LED/ 5-6
5.12 TolerANT Technology Electrical Characteristics for SE
SCSI Signals
5-7
5.13 External Clock 5-9
5.14 Reset Input 5-10
5.15 Interrupt Output 5-10
5.16 NVSRAM Read Cycle Timing 5-11
5.17 NVSRAM Write Cycle 5-13
5.18 Flash ROM Read Cycle Timing 5-15
5.19 Flash ROM Write Cycle 5-16
A.1 LSI53C1030 PCI Registers A-1