Figure5.7 interrupt output, 4 external memory timing diagrams, 1 nvsram timing – Avago Technologies LSI53C1030 User Manual
Page 135: Table 5.16 nvsram read cycle timing, External memory timing diagrams, Nvsram timing, Interrupt output, Nvsram read cycle timing, Section 5.4, “external memory timing diagrams, Figure 5.7
External Memory Timing Diagrams
5-11
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 5.7
Interrupt Output
5.4 External Memory Timing Diagrams
This section provides timing diagrams and data for NVSRAM and Flash
ROM timings.
5.4.1 NVSRAM Timing
and
provide the timing information for the Memory
Address and Data (MAD) bus NVSRAM read accesses.
t
1
t
2
t
3
IRQ/
CLK
Table 5.16
NVSRAM Read Cycle Timing
Symbol
Parameter
Min
Max
Unit
t
1
Address setup to FLSHALE/ HIGH
25
–
ns
t
2
Address hold from FLSHALE/ HIGH
25
–
ns
t
3
FLSHALE/ pulse width
25
–
ns
t
4
Address valid to data clocked in
135
–
ns
t
5
RAMCE/ LOW to data clocked in
85
–
ns
t
6
MOE/ LOW to data clocked in
75
–
ns
t
7
Data setup to MOE/ HIGH
10
–
ns
t
8
Data setup to RAMCE/ HIGH
10
–
ns
t
9
Data hold from RAMCE/ HIGH
0
–
ns