Document Outline

• SPARC JPS1 Implementation Supplement: Fujitsu SPARC64V
  • Fujitsu Limited
  • Release 1.0, 1 July 2002
• Contents
• Overview
  • 1.1 Navigating the SPARC64V Implementation Supplement
  • 1.2 Fonts and Notational Conventions
  • 1.3 The SPARC64V processor
    • 1.3.1 Component Overview
    • 1.3.2 Instruction Control Unit (IU)
    • 1.3.3 Execution Unit (EU)
    • 1.3.4 Storage Unit (SU)
    • 1.3.5 Secondary Cache and External Access Unit (SXU)
• Definitions
• Architectural Overview
• Data Formats
• Registers
  • 5.1 Nonprivileged Registers
    • 5.1.7 Floating-Point State Register (FSR)
    • 5.1.9 Tick (TICK) Register
  • 5.2 Privileged Registers
    • 5.2.6 Trap State (TSTATE) Register
    • 5.2.9 Version (VER) Register
    • 5.2.11 Ancillary State Registers (ASRs)
    • 5.2.12 Registers Referenced Through ASIs
    • 5.2.13 Floating-Point Deferred-Trap Queue (FQ)
    • 5.2.14 IU Deferred-Trap Queue
• Instructions
  • 6.1 Instruction Execution
    • 6.1.1 Data Prefetch
    • 6.1.2 Instruction Prefetch
    • 6.1.3 Syncing Instructions
  • 6.2 Instruction Formats and Fields
  • 6.3 Instruction Categories
    • 6.3.3 Control-Transfer Instructions (CTIs)
    • 6.3.7 Floating-Point Operate (FPop) Instructions
    • 6.3.8 Implementation-Dependent Instructions
  • 6.4 Processor Pipeline
    • 6.4.1 Instruction Fetch Stages
    • 6.4.2 Issue Stages
    • 6.4.3 Execution Stages
    • 6.4.4 Completion Stages
• Traps
  • 7.1 Processor States, Normal and Special Traps
    • 7.1.1 RED_state
    • 7.1.2 error_state
  • 7.2 Trap Categories
    • 7.2.2 Deferred Traps
    • 7.2.4 Reset Traps
    • 7.2.5 Uses of the Trap Categories
  • 7.3 Trap Control
    • 7.3.1 PIL Control
  • 7.4 Trap-Table Entry Addresses
    • 7.4.2 Trap Type (TT)
    • 7.4.4 Details of Supported Traps
  • 7.5 Trap Processing
  • 7.6 Exception and Interrupt Descriptions
    • 7.6.4 SPARC V9 Implementation-Dependent, Optional Traps That Are Mandatory in SPARC JPS1
    • 7.6.5 SPARC JPS1 Implementation-Dependent Traps
• Memory Models
  • 8.1 Overview
  • 8.4 SPARC V9 Memory Model
    • 8.4.5 Mode Control
    • 8.4.6 Synchronizing Instruction and Data Memory
• Instruction Definitions: SPARC64 V Extensions
  • A.4 Block Load and Store Instructions (VIS I)
  • A.12 Call and Link
  • A.24 Implementation-Dependent Instructions
    • A.24.1 Floating-Point Multiply-Add/Subtract
  • A.29 Jump and Link
  • A.30 Load Quadword, Atomic [Physical]
  • A.35 Memory Barrier
  • A.42 Partial Store (VIS I)
  • A.49 Prefetch Data
  • A.51 Read State Register
  • A.70 SHUTDOWN (VIS I)
  • A.70 Write State Register
  • A.71 Deprecated Instructions
    • A.71.10 Store Barrier
• IEEE Std 754-1985 Requirements for SPARC V9
  • B.1 Traps Inhibiting Results
  • B.6 Floating-Point Nonstandard Mode
    • B.6.1 fp_exception_other Exception (ftt=unfinished_FPop)
    • B.6.2 Operation Under FSR.NS = 1
• Implementation Dependencies
  • C.1 Definition of an Implementation Dependency
  • C.2 Hardware Characteristics
  • C.3 Implementation Dependency Categories
  • C.4 List of Implementation Dependencies
• Formal Specification of the Memory Models
• Opcode Maps
• Memory Management Unit
  • F.1 Virtual Address Translation
  • F.2 Translation Table Entry (TTE)
    • F.3.3 TSB Organization
    • F.4.2 TSB Pointer Formation
  • F.5 Faults and Traps
  • F.8 Reset, Disable, and RED_state Behavior
  • F.10 Internal Registers and ASI operations
    • F.10.1 Accessing MMU Registers
    • F.10.4 I/D TLB Data In, Data Access, and Tag Read Registers
    • F.10.7 I/D TSB Extension Registers
    • F.10.9 I/D Synchronous Fault Status Registers (I-SFSR, D-SFSR)
  • F.11 MMU Bypass
    • F.11.10 TLB Replacement Policy
• Assembly Language Syntax
• Software Considerations
• Extending the SPARC V9 Architecture
• Changes from SPARC V8 to SPARC V9
• Programming with the Memory Models
• Address Space Identifiers
  • L.3 SPARC64 V ASI Assignments
    • L.3.2 Special Memory Access ASIs
  • L.4 Barrier Assist for Parallel Processing
    • L.4.1 Interface Definition
    • L.4.2 ASI Registers
• Cache Organization
  • M.1 Cache Types
    • M.1.1 Level-1 Instruction Cache (L1I Cache)
    • M.1.2 Level-1 Data Cache (L1D Cache)
    • M.1.3 Level-2 Unified Cache (L2 Cache)
  • M.2 Cache Coherency Protocols
  • M.3 Cache Control/Status Instructions
    • M.3.1 Flush Level-1 Instruction Cache (ASI_FLUSH_L1I)
    • M.3.2 Level-2 Cache Control Register (ASI_L2_CTRL)
    • M.3.3 L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ)
    • M.3.4 L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG)
• Interrupt Handling
  • N.1 Interrupt Dispatch
  • N.2 Interrupt Receive
  • N.3 Interrupt Global Registers
  • N.4 Interrupt-Related ASR Registers
    • N.4.2 Interrupt Vector Dispatch Register
    • N.4.3 Interrupt Vector Dispatch Status Register
    • N.4.5 Interrupt Vector Receive Register
• Reset, RED_state, and error_state
  • O.1 Reset Types
    • O.1.1 Power-on Reset (POR)
    • O.1.2 Watchdog Reset (WDR)
    • O.1.3 Externally Initiated Reset (XIR)
    • O.1.4 Software-Initiated Reset (SIR)
  • O.2 RED_state and error_state
    • O.2.1 RED_state
    • O.2.2 error_state
    • O.2.3 CPU Fatal Error state
  • O.3 Processor State after Reset and in RED_state
    • O.3.1 Operating Status Register (OPSR)
    • O.3.2 Hardware Power-On Reset Sequence
    • O.3.3 Firmware Initialization Sequence
• Error Handling
  • P.1 Error Classification
    • P.1.1 Fatal Error
    • P.1.2 error_state Transition Error
    • P.1.3 Urgent Error
    • P.1.4 Restrainable Error
  • P.2 Action and Error Control
    • P.2.1 Registers Related to Error Handling
    • P.2.2 Summary of Actions Upon Error Detection
    • P.2.3 Extent of Automatic Source Data Correction for Correctable Error
    • P.2.4 Error Marking for Cacheable Data Error
    • P.2.5 ASI_EIDR
    • P.2.6 Control of Error Action (ASI_ERROR_CONTROL)
  • P.3 Fatal Error and error_state Transition Error
    • P.3.1 ASI_STCHG_ERROR_INFO
    • P.3.2 Fatal Error Types
    • P.3.3 Types of error_state Transition Errors
  • P.4 Urgent Error
    • P.4.1 URGENT ERROR STATUS (ASI_UGESR)
    • P.4.2 Action of async_data_error (ADE) Trap
    • P.4.3 Instruction End-Method at ADE Trap
    • P.4.4 Expected Software Handling of ADE Trap
  • P.5 Instruction Access Errors
  • P.6 Data Access Errors
  • P.7 Restrainable Errors
    • P.7.1 ASI_ASYNC_FAULT_STATUS (ASI_AFSR)
    • P.7.2 ASI_ASYNC_FAULT_ADDR_D1
    • P.7.3 ASI_ASYNC_FAULT_ADDR_U2
    • P.7.4 Expected Software Handling of Restrainable Errors
  • P.8 Handling of Internal Register Errors
    • P.8.1 Register Error Handling (Excluding ASRs and ASI Registers)
    • P.8.2 ASR Error Handling
    • P.8.3 ASI Register Error Handling
  • P.9 Cache Error Handling
    • P.9.1 Handling of a Cache Tag Error
    • P.9.2 Handling of an I1 Cache Data Error
    • P.9.3 Handling of a D1 Cache Data Error
    • P.9.4 Handling of a U2 Cache Data Error
    • P.9.5 Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache
  • P.10 TLB Error Handling
    • P.10.1 Handling of TLB Entry Errors
    • P.10.2 Automatic Way Reduction of sTLB
  • P.11 Handling of Extended UPA Bus Interface Error
    • P.11.1 Handling of Extended UPA Address Bus Error
    • P.11.2 Handling of Extended UPA Data Bus Error
• Performance Instrumentation
  • Q.1 Performance Monitor Overview
    • Q.1.1 Sample Pseudocodes
  • Q.2 Performance Monitor Description
    • Q.2.1 Instruction Statistics
    • Q.2.2 Trap-Related Statistics
    • Q.2.3 MMU Event Counters
    • Q.2.4 Cache Event Counters
    • Q.2.5 UPA Event Counters
    • Q.2.6 Miscellaneous Counters
• UPA Programmer’s Model
  • R.1 Mapping of the CPU’s UPA Port Slave Area
  • R.2 UPA PortID Register
  • R.3 UPA Config Register
• Summary of Differences between SPARC64 V and UltraSPARC-III
• Bibliography
  • General References