FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 193)

182 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
P.8.2 ASR Error Handling
The terminology used in TABLE P-19 is defined as follows:
TABLE P-19 shows the handling of ASR errors.
TPC RW Parity InstAccess IUG_TSTATE W
TNPC RW Parity InstAccess IUG_TSTATE W
TSTATE RW Parity InstAccess IUG_TSTATE W
WSTATE RW Parity InstAccess IUG_TSTATE W
VER R None — — —
FSR RW Parity Always IUG_%F ADE trap, W
Column Term Meaning
Error Detect
Condition AUG always The error is detected while
(
ASI_ERROR_CONTROL.UGE_HANDLER = 0) &&
( ASI_ERROR_CONTROL.WEAK_ED = 0)
InstAccess The error is detected when the instruction accesses the
register.
Error Type (I)AUG _xxx The error is indicated by ASI_UGESR.IAUG_ xxx = 1, and
the error is an autonomous urgent error.
I(A)UG _xxx The error is indicated by ASI_UGESR.IAUG_ xxx = 1, and
the error is an instruction urgent error.
Correction W The error is removed by a full write to the register by an
instruction.
ADE trap The error is removed by a full write to the register in the
async_data_error hardware trap sequence.
TABLE P-19 ASR Error Handling
ASR
Number Register Name
RW Error Protect Error Detect Condition Error Type Correction
0 Y RW Parity InstAccess IUG_%R W
1 —
2 CCR RW Parity Always IUG_%R ADE trap, W
3 ASI RW Parity Always IUG_%R ADE trap, W
4 TICK RW None — — —
TABLE P-18 Register Error Handling (Excluding ASRs and ASI Registers)
Register Name RW
Error
Protect
Error Detect Condition Error Type Correction