FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 57)

46 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
4. A description of the features, restrictions, and exception-causing conditions.
5. A list of exceptions that can occur as a consequence of attempting to execute the
instruction(s). Exceptions due to an instruction_access_error ,
instruction_access_exception , fast_instruction_access_MMU_miss , async_data_error ,
ECC_error , and interrupts are not listed because they can occur on any instruction.
Also, any instruction that is not implemented in hardware shall generate an
illegal_instruction exception (or fp_exception_other exception with
ftt = unimplemented_FPop for floating-point instructions) when it is executed.
The illegal_instruction trap can occur during chip debug on any instruction that has
been programmed into the processor’s IIU_INST_TRAP (ASI = 60
16
, VA = 0).
These traps are also not listed under each instruction.
The following traps never occur in SPARC64 V:
■ instruction_access_MMU_miss
■ data_access_MMU_miss
■ data_access_protection
■ unimplemented_LDD
■
unimplemented_STD
■
LDQF_mem_address_not_aligned
■ STQF_mem_address_not_aligned
■ internal_processor_error
■ fp_exception_other ( ftt = invalid_fp_register )
This appendix does not include any timing information (in either cycles or clock
time).
The following SPARC64 V-specific extensions are described.
■
Block Load and Store Instructions (VIS I) on page 47
■ Call and Link on page 49
■ Implementation-Dependent Instructions on page 49
■ Jump and Link on page 53
■ Load Quadword, Atomic [Physical] on page 54
■
Memory Barrier on page 55
■ Partial Store (VIS I) on page 57
■
Prefetch Data on page 57
■ Read State Register on page 58
■ SHUTDOWN (VIS I) on page 58
■ Write State Register on page 59
■ Deprecated Instructions on page 59