FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 42)

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 31
6.4 Processor Pipeline
The pipeline of SPARC64 V consists of fifteen stages, shown in FIGURE 6-2. Each
stage is referenced by one or two letters as follows:
6.4.1 Instruction Fetch Stages
■ IA (Instruction Address generation) — Calculate fetch target address.
■
IT (Instruction TLB Tag access) — Instruction TLB tag search. Search of BRHIS
and RAS is also started.
■ IM (Instruction TLB tag Match) — Check TLB tag is matched.
The result of BRHIS and RAS search is also available at this stage and is
forwarded to IA stage for subsequent fetch.
■ IB (Instruction cache Buffer read) — Read L1 cache data if TLB is hit.
■ IR (Instruction read Result) — Write to I-Buffer.
IA through IR stages are dedicated to instruction fetch. These stages work in concert
with the cache access unit to supply instructions to subsequent stages. The
instructions fetched from memory or cache are stored in the Instruction Buffer (I-
buffer). The I-buffer has six entries, each of which can hold 32-byte-aligned 32-byte
data (eight instructions).
SPARC64 V has a branch prediction mechanism and resources named BRHIS
(BRanch HIStory) and RAS (Return Address Stack). Instruction fetch stages use these
resources to determine fetch addresses.
Instruction fetch stages are designed so that they work independently of subsequent
stages as much as possible. And they can fetch instructions even when execution
stages stall. These stages fetch until the I-Buffer is full; further fetches are possible by
requesting prefetches to the L1 cache.
IA IT IM IB IR
E D P B X U W
Ps Ts Ms Bs Rs