FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 64)

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 53
Programming Note – The Multiply Add/Subtract instructions are encoded in the
SPARC V9 IMPDEP2 opcode space, and they are specific to the SPARC64 V
implementation. They cannot be used in any programs that will be executed on any
other SPARC V9 processor, unless that implementation exactly matches the
SPARC64 V use for the
IMPDEP2 opcode.
Exceptions fp_disabled
fp_exception_ieee_754
(NV, NX, OF, UF)
illegal_instruction (size = 00
2
or 11
2
) ( fp_disabled is not checked for these encodings)
fp_exception_other ( unfinished_FPop )
A.29 Jump and Link
SPARC64 V clears the upper 32 bits of the PC value in r[rd ] when PSTATE.AM is set
(impl. dep. #125). The value written into r[rd] is visible to the instruction in the
delay slot.
If either of the low-order two bits of the jump address is nonzero, a
mem_address_not_aligned exception occurs. However, when the JMPL instruction
causes a mem_address_not_aligned trap, DSFSR and DSFAR are not updated.
If the JMPL instruction has r[rd] = 15, SPARC64 V stores PC + 8 in a hardware table
called return address stack (RAS). When a ret ( jmpl %i7+8, %g0 ) or retl ( jmpl
%o7+8, %g0 ) is executed, the value in the RAS is used to predict the return address.
JMPL with rd = 0 can be used to return from a subroutine. The typical return
address is “ r[31] + 8 ” if a nonleaf routine (one that uses the SAVE instruction) is
entered by a CALL instruction, or “ r[15] + 8 ” if a leaf routine (one that does not
use the SAVE instruction) is entered by a CALL instruction or by a JMPL instruction
with rd = 15.