FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 14)

Release 1.0, 1 July 2002 F. Chapter 1 Overview 3
1. Advanced RAS features for caches
■ Strong cache error protection:
■
ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data,
and the U2 cache tag.
■
Parity protection for I1 (Instruction level 1) cache data.
■
Parity protection and duplication for the I1 cache tag and the D1 cache tag.
■ Automatic correction of all types of single-bit error:
■
Automatic single-bit error correction for the ECC protected data.
■
Invalidation and refilling of I1 cache data for the I1 cache data parity error.
■
Copying from duplicated tag for I1 cache tag and D1 cache tag parity errors.
■ Dynamic way reduction while cache consistency is maintained.
■ Error marking for cacheable data uncorrectable errors:
■
Special error-marking pattern for cacheable data with uncorrectable errors. The
identification of the module that first detects the error is embedded in the
special pattern.
■
Error-source isolation with faulty module identification in the special error-
marking. The identification information enables the processor to avoid
repetitive error logging for the same error cause.
2. Advanced RAS features for the core
■ Strong error protection:
■
Parity protection for all data paths.
■
Parity protection for most of software-visible registers and internal temporary
registers.
■
Parity prediction or residue checking for the accumulator output.
■ Hardware instruction retry
■ Support for software instruction retry (after failure of hardware instruction retry)
■ Error isolation for software recovery:
■
Error indication for each programmable register group.
■
Indication of retryability of the trapped instruction.
■
Use of different error traps to differentiate degrees of adverse effects on the
CPU and the system.
3. Extended RAS interface to software
■ Error classification according to the severity of the effect on program execution:
■
Urgent error (nonmaskable): Unable to continue execution without OS
intervention; reported through a trap.
■
Restrainable error (maskable): OS controls whether the error is reported
through a trap, so error does not directly affect program execution.
■ Isolated error indication to determine the effect on software