FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 191)

180 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
b. Write the U2 cache line with the CE detection to memory either by using the
ASI_L2_CTRL.U2_FLUSH facility or by displacement flush.
c. Clear ASI_AFSR.CE_INCOMED and reload the memory block to U2 cache,
using load instructions. Check whether the CE in memory has been corrected
by inspecting
ASI_AFSR.CE_INCOMED and ASI_AFAR_U2 .
d. If the CE in memory block is not corrected, a permanent error may be detected.
Avoid using the memory block with the permanent correctable error as much
as possible.
■ ASI_AFSR.UE_DST_BETO — This error is caused by either:
■
Invalid DTLB entry is specified, or
■
Invalid memory access instruction with physical address access ASI is executed
in privileged software.
This error is always caused by a mistake in privileged software. Record the error
and correct the erroneous privileged software.
■ ASI_AFSR.UE_RAW_L2$FILL , UE_RAW_L2$INSD , and UE_RAW_D1$INSD — Software
handles these errors as follows:
■
Correct the cache line data containing the uncorrected error by executing a
block store with commit instruction, if possible. Note that the original data is
deleted by this operation.
■
For UE_RAW_L2$FILL , avoid using the memory block with the UE as much as
possible.
■ No error indication in ASI_AFSR at ECC_error trap — Ignore the ECC_error trap.
This situation may occur at the condition described in the TABLE P-2 on page 154
(see the third row, last column, and “Deviation from the ideal specification”).