FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 152)

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 141
O.2.3 CPU Fatal Error state
The processor enters CPU fatal error state when a fatal error is detected on the
processor. A fatal error is one that breaks the cache coherency or the system data
integrity and is not reported as the SDC (small data corruption) error. See Appendix
P, Error Handling, for details of the SDC error.
The processor reports the fatal error detection to the system, and the system causes
the fatal reset. Soft POR will be applied to the all CPUs in the system at the fatal
reset.
O.3 Processor State after Reset and in
RED_state
TABLE O-1 shows the various processor states after resets and when entering
RED_state .
In this table, it is assumed that RED_state entry happens as a result of resets or
traps. If RED_state entry occurs because the WRPR instruction sets the PSTATE.RED
bit, no processor state will be changed except the PSTATE.RED bit itself; the effects
of this are described in RED_state on page 140.
TABLE O-1 Nonprivileged and Privileged Register State after Reset and in RED_state
Name POR 1 WDR 2 XIR SIR RED_state
Integer registers Unknown/Unchanged Unchanged
Floating Point registers Unknown/Unchanged Unchanged
RSTV value VA = FFFF FFFF F000 0000
16
PA = 07FF F000 0000 16 (43-bit PA mode specified by OPSR . )
PC
nPC
RSTV | 20
16
RSTV | 2 4
16
RSTV | 40
16
RSTV | 44
16
RSTV | 60
16
RSTV | 64
16
RSTV | 80
16
RSTV | 84
16
RSTV | A0
16
RSTV | A4
16
PSTATE AG
MG
IG
IE
PRIV
AM
PEF
RED
MM
1 (Alternate globals)
0 (MMU globals not selected)
0 (Interrupt globals not selected)
0 (Interrupt disable)
1 (Privileged mode)
0 (Full 64-bit address)
1 (FPU on)
1 (Red_state)
00 (TSO)