FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 18)

Release 1.0, 1 July 2002 F. Chapter 1 Overview 7
1.3.4 Storage Unit (SU)
The SU handles all sourcing and sinking of data for load and store instructions.
TABLE 1-3 describes the SU major blocks.
Interface registers Input/output registers to other units.
Two integer execution pipelines
(EXA, EXB) 64-bit ALU and shifters.
Two floating-point and graphics
execution pipelines (FLA, FLB) Each floating-point execution pipeline can execute floating
point multiply, floating point add/sub, floating-point
multiply and add, floating point div/sqrt, and floating-
point graphics instruction.
Two virtual address adders for
memory access pipeline (
EAGA ,
EAGB )
Two 64-bit virtual addresses for load/store.
TABLE 1-3 Storage Unit Major Blocks
Name Description
Instruction level-1 cache 128-Kbyte, 2-way associative, 64-byte line; provides low latency
instruction source
Data level-1 cache 128-Kbyte, 2-way associative, 64-byte line, writeback; provides
the low latency data source for loads and stores.
Instruction Translation
Buffer 1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages
1 ,
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte 1 pages and locked pages in all sizes.
1. Unloced 4-Mbyte page entry is stored either in 2-way associative TLB or fully associative
TLB exclusively, depending on the setting.
Data Translation Buffer 1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages
1 ,
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte 1 pages and locked pages in all sizes.
Store queue Decouples the pipeline from the latency of store operations.
Allows the pipeline to continue flowing while the store waits for
data, and eventually writes into the data level 1 cache.
TABLE 1-2 Execution Unit Major Blocks (Continued)
Name Description