FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 210)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 199
■ Incoming noncacheable data fetched by an instruction fetch. When a UE is
detected in such data, an instruction_access_error with marked UE is detected at the
time the fetched instruction is executed.
■ Incoming noncacheable data loaded by a load instruction. When the UE is
detected in such data, a data_access_error with marked UE is detected at the time
the load instruction is executed.
■ Incoming cacheable data fetched by an instruction fetch. When the UE is
detected in such data, the target U2 cache line is filled with the marked UE data
and the target I1 cache line is filled with the parity error data. The
instruction_access_error is detected when the fetched instruction is executed, as
described in Handling of an I1 Cache Data Error on page 190.
■
Incoming cacheable data accessed by a load or store instruction. When the UE is
detected in such data, the target U2 cache line and the target D1 cache line are
filled with the marked
UE data. The data_access_error is detected when the load or
store instruction (excluding doubleword store) is executed, as described in Marked
Uncorrectable Error in D1 Cache Data on page 191.
UE in Outgoing Data to Extended UPA Data Bus
At the time data is sent to the extended UPA bus, a SPARC64 V processor handles a
UE in data outgoing data, as follows:
■ Marked UE in outgoing data to the extended UPA data bus. When the processor
detects such data, the processor transfers the data without modification and does
not report the error to software on the processor.
■ Raw UE in outgoing data to the extended UPA data bus. When the processor
detects such data, the processor applies error marking to the outgoing data. The
data is changed to marked
UE with ERROR_MARK_ID = ASI_EIDR , indicating the
processor causing error. The marked UE data is then transferred to the destination.
Note – The destination always receives marked UE data for both marked UE and raw
UE in outgoing data from the processor to the extended UPA data bus, as described
above.
Finally, the treatment of an uncorrectable error ( UE ) in outgoing data to the extended
UPA bus depends on whether the access was to cacheable or noncacheable data, as
follows:
■ Outgoing noncacheable data with UE detected. When a UE is detected in such
data, no error is reported on the source processor but error reporting from the
destination UPA port is expected.
■ Outgoing cacheable data with UE detected. When a UE is detected in such data,
the processor transfers the marked UE data to the destination memory or cache.
When the marked UE data is used by a processor or a channel, the error will be
reported to software.