FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 164)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 153
■ Degradation
SPARC64 V can isolate an internal hardware resource that generates frequent
errors and continue processing without deleterious effect on software during
program execution. However, performance is degraded by the resource isolation.
This degradation is reported as a restrainable error.
The restrainable error can be reported to privileged software by the ECC_error trap.
When PSTATE.IE = 1 and the trap enable mask for any restrainable error is 1, the
ECC_error exception is generated for the restrainable error.
P.2 Action and Error Control
P.2.1 Registers Related to Error Handling
The following registers are related to the error handling.
■ ASI registers: Indicate an error. All ASI registers in TABLE P-1 except ASI_EIDR
and ASI_ERROR_CONTROL are used to specify the nature of an error to privileged
software.
■ ASI_ERROR_CONTROL : Controls error action. This register designates error
detection masks and error trap enable masks.
■ ASI_EIDR : Marks errors. This register identifies the error source ID for error
marking.
TABLE P-1 lists the registers related to error handling.
TABLE P-1 Registers Related to Error Handling
ASI VA R/W Checking Code Name Defined in
4C
16
00
16
RW1C None ASI_ASYNC_FAULT_STATUS P.7.1
4C
16
08
16
R None ASI_URGENT_ERROR_STATUS P.4.1
4C
16
10
16
RW Parity ASI_ERROR_CONTROL P.2.1
4C
16
18
16
R,W1AC None ASI_STCHG_ERROR_INFO P.3.1
4D
16
00
16
RW1AC Parity ASI_ASYNC_FAULT_ADDR_D1 P.7.2
4D
16
08
16
RW1AC Parity ASI_ASYNC_FAULT_ADDR_U2 P.7.3
50
16
18
16
RW None ASI_IMMU_SFSR F.10.9
58
16
18
16
RW None ASI_DMMU_SFSR F.10.9
58
16
20
16
RW Parity ASI_DMMU_SFAR F.10.10 of Commonality
6E
16
00
16
RW Parity ASI_EIDR P.2.5