FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 134)

Release 1.0, 1 July 2002 F. Chapter L Address Space Identifiers 123
BSTW Control Register ( ASI_C_BSTW0 , ASI_C_BSTW1 )
The BSTW control register designates which bit in LBSY is written through
ASI_BSTW x.
BSTW Busy Status Register ( ASI_C_BSTWBUSY )
The BSTW busy status register indicates an update is made to LBSY in the SB and has
not completed yet.
Programming Note – Supervisor software should not write to ASI_C_BSTW x
while ASI_C_BSTWBUSY.BUSY = 1. Otherwise, subsequent writes are ignored or a
write to wrong BST is sent to the SB.
[1] Register Name: ASI_C_BSTW0 , ASI_C_BSTW1
[2] ASI: 6F
16
[3] VA: 80
16
( ASI_C_BSTW0 ), 88
16
( ASI_C_BSTW1 ).
[4] RW Supervisor read/write
Bit Name RW Description
63 V RW Valid. When V = 0, BL_num and SB_BPU_num are
ignored and a write to ASI_BSTW x is discarded. When
V = 1, data in the ASI_BSTW x is written to the selected
bit in SB_BPU .
6 SB_BPU_num RW SB BPU number on the SB.
5:0 BST_num RW BST bit number in the selected SB BPU.
[1] Register Name: ASI_C_LBSTWBUSY
[2] ASI: 6F
16
[3] VA: C0
16
[4] RW Supervisor read
Bit Name RW Description
0 BUSY R BUSY = 1 is indicated when a write to ASI_C_BSTWx is made
but LBSY on the SB has not yet been updated.