FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual
Page 90
Release 1.0, 1 July 2002
F. Chapter C
Implementation Dependencies
79
240
DCU Control Register bits 47:41
SPARC64 V
uses bit 41 for
WEAK_SPCA
, which enables/disables memory
access in speculative paths.
241
Address Masking and
DSFAR
SPARC64 V
writes zeroes to the more significant 32 bits of
DSFAR
.
—
242
TLB lock bit
In SPARC64 V, only the fITLB and the fDTLB support the lock bit. The lock
bit in sITLB and sDTLB is read as 0 and writes to it are ignored.
243
Interrupt Vector Dispatch Status Register BUSY/NACK pairs
In
SPARC64 V
, 32 BUSY/NACK pairs are implemented in the Interrupt
Vector Dispatch Status Register.
244
Data Watchpoint Reliability
No implementation-dependent features of
SPARC64 V
reduce the reliability
of data watchpoints.
245
Call/Branch displacement encoding in I-Cache
In
SPARC64 V
, the least significant 11 bits (bits 10:0) of a
CALL
or branch
(
BPcc
,
FBPfcc
,
Bicc
,
BPr
) instruction in an instruction cache are identical
to the architectural encoding (as they appear in main memory).
246
VA
<38:29> for Interrupt Vector Dispatch Register Access
SPARC64 V
ignores all 10 bits of
VA
<38:29> when the Interrupt Vector
Dispatch Register is written.
247
Interrupt Vector Receive Register SID fields
SPARC64 V
obtains the interrupt source identifier
SID_L
from the UPA
packet.
248
Conditions for
fp_exception_other
with
unfinished_FPop
SPARC64 V
triggers
fp_exception_other
with trap type
unfinished_FPop
under the standard conditions described in Commonality Section 5.1.7.
249
Data watchpoint for Partial Store instruction
Watchpoint exceptions on Partial Store instructions occur conservatively on
SPARC64 V
. The
DCUCR
Data Watchpoint masks are only checked for
nonzero value (watchpoint enabled). The byte store mask (
r[rs2]
) in the
Partial Store instruction is ignored, and a watchpoint exception can occur
even if the mask is zero (that is, no store will take place).
250
PCR
accessibility when
PSTATE.PRIV
= 0
In
SPARC64 V
, the accessibility of
PCR
when
PSTATE.PRIV
= 0 is
determined by
PCR.PRIV
. If
PSTATE.PRIV
= 0 and
PCR.PRIV
= 1, an
attempt to execute either
RDPCR
or
WRPCR
will cause a
privileged_action
exception. If
PSTATE.PRIV
= 0 and
PCR.PRIV
= 0,
RDPCR
operates without
privilege violation and
WRPCR
generates a
privileged_action
exception only
when an attempt is made to change (that is, write 1 to)
PCR.PRIV
.
251
Reserved.
—
TABLE C-1
SPARC64 V Implementation Dependencies (10 of 11)
Nbr
SPARC64 V Implementation Notes
Page