FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 86)

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 75
119 Unimplemented values for PSTATE.MM
Writing 11
2
into PSTATE.MM causes the machine to use the TSO memory
model. However, the encoding 11
2
should not be used, since future versions
of SPARC64 V may use this encoding for a new memory model.
42
120 Coherence and atomicity of memory operations
Although SPARC64 V implements the UPA-based cache coherency
mechanism, this dependency is beyond the scope of this publication. It
should be defined in a system that uses
SPARC64 V .
—
121 Implementation-dependent memory model
SPARC64 V implements TSO, PSO, and RMO memory models. See
Chapter 8, Memory Models, for details.
Accesses to pages with the
E (Volatile) bit of their MMU page table entry set
are also made in program order.
—
122 FLUSH latency
Since the FLUSH instruction synchronizes the processor, its total latency
varies depending on many portions of the SPARC64 V processor ’s state.
Assuming that all prior instructions are completed, the latency of
FLUSH is
18 processor cycles .
—
123 Input / output (I/O) semantics
This dependency is beyond the scope of this publication. It should be
defined in a system that uses
SPARC64 V .
—
124 Implicit ASI when TL > 0
See Section 5.1.7 of Commonality for details.
—
125 Address masking
When
PSTATE.AM = 1, SPARC64 V does mask out the high-order 32 bits of
the PC when transmitting it to the destination register.
29, 49, 53
126 Register Windows State Registers width
NWINDOWS for SPARC64 V is 8; therefore, only 3 bits are implemented for
the following registers: CWP , CANSAVE , CANRESTORE , OTHERWIN . If an
attempt is made to write a value greater than NWINDOWS
−
1 to any of these
registers, the extraneous upper bits are discarded. The CLEANWIN register
contains 3 bits.
—
127–201 Reserved.
202 fast_ECC_error trap
fast_ECC_error trap is not implemented in SPARC64 V .
—
203 Dispatch Control Register bits 13:6 and 1
SPARC64 V does not implement DCR .
22
204 DCR bits 5:3 and 0
SPARC64 V does not implement DCR .
22
205 Instruction Trap Register
SPARC64 V implements the Instruction Trap Register.
24
TABLE C-1 SPARC64 V Implementation Dependencies (6 of 11)
Nbr SPARC64 V Implementation Notes Page