FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 197)

186 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
TABLE P-20 shows the handling of ASI register errors.
TABLE P-20 Handling of ASI Register Errors
ASI VA
Register Name RW
Error
Protect Error Detect
Condition
Error Type Correction
45
16
00
16
DCU_CONTROL RW Parity Always error_state RED trap
08
16
MEMORY_CONTROL RW Parity Always error_state RED trap
48
16
00
16
INTR_DISPATCH_STATUS R Gecc LDXA I(A)UG_CRE ( UE )
ignored ( CE )
None
49
16
00
16
INTR_RECEIVE RW Gecc LDXA I(A)UG_CRE ( UE )
ignored ( CE )
None
4A
16
— UPA_CONFIGUATION R None — — —
4C
16
00
16
ASYNC_FAULT_STATUS RW1C None — — —
4C
16
08
16
URGENT_ERROR_STATUS R None — — —
4C
16
10
16
ERROR_CONTROL RW Parity Always error_state RED trap
4C
16
18
16
STCHG_ERROR_INFO R,W1AC None — — —
4D
16
00
16
AFAR_D1 R,W1AC Parity LDXA I(A)UG_CRE W1AC
4D
16
08
16
AFAR_U2 R,W1AC Parity LDXA I(A)UG_CRE W1AC
50
16
00
16
IMMU_TAG_TARGET R Parity LDXA #I IUG_TSBP WotherI
50
16
18
16
IMMU_SFSR RW None — — —
50
16
28
16
IMMU_TSB_BASE RW Parity LDXA #I I(A)UG_TSBCTXT W
50
16
30
16
IMMU_TAG_ACCESS RW Parity LDXA #I IUG_TSBP W (WotherI)
50
16
48
16
IMMU_TSB_PEXT RW Parity = ITSB_BASE IAUG_TSBCTXT W
50
16
58
16
IMMU_TSB_NEXT R Parity = ITSB_BASE IAUG_TSBCTXT W
51
16
— IMMU_TSB_8KB_PTR R PP LDXA IUG_TSBP WotherI
52
16
— IMMU_TSB_64KB_PTR R PP LDXA IUG_TSBP WotherI
53
16
— SERIAL_ID R None — — —
54
16
— ITLB_DATA_IN W Parity ITLB write IUG_ITLB DemapAll
55
16
— ITLB_DATA_ACCESS RW Parity LDXA
ITLB write
IUG_ITLB
IUG_ITLB DemapAll
DemapAll
56
16
— ITLB_TAG_READ R Parity LDXA IUG_ITLB DemapAll
57
16
— IMMU_DEMAP W Parity ITLB write IUG_ITLB DemapAll
58
16
00
16
DMMU_TAG_TARGET R Parity LDXA #D IUG_TSBP WotherD
58
16
08
16
PRIMARY_CONTEXT RW Parity LDXA #I,
LDXA #D
Use for TLB
AUG always
I(A)UG_TSBCTXT
I(A)UG_TSBCTXT
(I)AUG_TSBCTXT
W
W
W
58
16
10
16
SECONDARY_CONTEXT RW Parity = P_CONTEXT IAUG_TSBCTXT W
58
16
18
16
DMMU_SFSR RW None — — —
58
16
20
16
DMMU_SFAR RW Parity LDXA IAUG_CRE W
58
16
28
16
DMMU_TSB_BASE RW Parity LDXA #D I(A)UG_TSBCTXT W