FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 172)

Release 1.0, 1 July 2002 F. Chapter P Error Handling 161
P.2.5 ASI_EIDR
The ASI_EIDR register designates the source ID in the ERROR_MARK_ID of the CPU.
P.2.6 Control of Error Action ( ASI_ERROR_CONTROL )
Error detection masking and the action after error detection are controlled by the
value in
ASI_ERROR_CONTROL , as defined in TABLE P-9.
The ASI_ERROR_CONTROL register controls error detection masking, error trap
occurrence masking, and the multiple- ADE trap occurrence. The register fields are
described in TABLE P-9 .
[1] Register name: ASI_EIDR
[2] ASI: 6E
16
[3] VA: 00
16
[4] Error checking: Parity.
[5] Format & function: See TABLE P-8 .
TABLE P-8 ASI_EIDR Bit Description
Bit Name RW Description
63:14 Reserved R Always 0.
13:0 ERROR_MARK_ID RW ERROR_MARK_ID for the error caused by the CPU.
[1] Register name: ASI_ERROR_CONTROL ( ASI_ECR )
[2] ASI: 4C
16
[3] VA: 10
16
[4] Error checking: None
[5] Format & function: See TABLE P-9 .
[6] Initial value at reset: Hard POR: ASI_ERROR_CONTROL.WEAK_ED is set to 1.
Other fields are set to 0.
Other resets: After
UGE_HANDLER and WEAK_ED are copied
into ASI_STCHG_ERROR_INFO , all fields in
ASI_ERROR_CONTROL are set to 0.
TABLE P-9 ASI_ERROR_CONTROL Bit Description
Bit Name RW Description
9 RTE_UE RW Restrainable Error Trap Enable submask for UE and Raw UE . The bit works as
defined in TABLE P-2 .
8 RTE_CEDG RW Restrainable Error Trap Enable submask for Corrected Error ( CE ) and
Degradation ( DG ). The bit works as defined in TABLE P-2 .