FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual

Page 166

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Release 1.0, 1 July 2002

F. Chapter P

Error Handling

155

Action upon the
error detection

1. CPU enters

CPU fatal
state.

2. CPU informs

the system of
fatal error
occurrence.

3. The FATAL

reset (which is
a form of POR
reset) is issued
to the whole
system.

4. POR reset is

caused to all
CPUs in the
system.

1. CPU enters

error_state

.

2. Watchdog reset

(WDR) is caused
on the CPU.

Detection of

I_UGE

When

ASI_ECR.UGE_HANDLER

= 0,

a single-

ADE

trap is caused.

Otherwise, when

ASI_ECR.UGE_HANDLER

= 1,

a multiple-

ADE

trap is caused.

Detection of

A_UGE

When the trap is enabled, a
single-

ADE

trap is caused.

When the trap is disabled, the
trap condition is kept pending
in hardware.

Detection of

IAE

When

ASI_ECR.UGE_HANDLER

= 0,

an

IAE

trap is caused. Other-

wise, a multiple-

ADE

trap is

caused.

Detection of

DAE

When

ASI_ECR.UGE_HANDLER

= 0,

a

DAE

trap is caused. Other-

wise, a multiple-

ADE

trap is

caused.

Ideal specification

1. The error detection is kept

pending in one bit of

ASI_AFSR

.

2. When the trap condition

for the pending error
detection is enabled, the

ECC_error

exception is

generated.

Deviation in SPARC64 V

An

ECC_error

trap can occur

even though

ASI_AFSR

does not indicate any
detected error(s)
corresponding to any trap-
enable bit (

RTE_UE

or

RTE_CEDG

) set to 1 in

ASI_ECR

, in the following

cases:

1. A pending detected error

is erased from

ASI_ASFR

(by writing

1

to

ASI_AFSR

) after the error

is detected but before the

ECC_error

trap is

generated.

2. A pending

CE

or

DG

is

erased by writing 1 to

ASI_AFSR

after the

ECC_error

trap is caused

by the

UE

error detection.

3. A pending

UE

is erased by

writing 1 to

ASI_AFSR

after the

ECC_error

trap is

caused by

CE

or

DG

detection.

Privileged software should
ignore an

ECC_error

trap

when the

AFSR

contains no

errors corresponding to
those enabled in

ASI_ECR

to cause a trap.

Priority of
action when
multiple types
of errors are
simultaneously
detected

1 — CPU fatal
state

2 —

error_state

3 —

ADE

trap

4 —

DAE

trap

5 —

IAE

trap

6 —

ECC_error

trap

TABLE P-2

Action Upon Detection of an Error (2 of 4)

Fatal Error (FE)

Error State Transition

Error (EE)

Urgent Error (UGE)

Restrainable Error (RE)

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